Jetson NX UART2 strange behaviour

I am using a Jetson NX with devkit carrier board (L4T 32.6.1) and currently using ttyTHS0 and ttyTHS1 serial ports just fine. I would like to convert the serial debug port into a normal uart port as I need a third serial port.

  • I disabled combined-uart and enabled serial@c280000 in the device tree
  • I removed the serial{} part in the bpmp

After the flash, /dev/ttyTHS2 appears in dmesg and in the filesystem.

When connecting ttyTHS0 and ttyTHS1 to my PC with a standard USB adapter, communication works correctly (using screen /dev/xxx 115200). When I type text in either terminal (pc or NX), characters are sent and received immediately by the other side.
Now if I do the same on /dev/ttyTHS2, communication is strange:

  1. For the Jetson TX pin: when I type text on the jetson terminal, I have to press a key on the pc terminal to receive what I typed, as if the Jetson NX had a ‘send buffer’ awaiting an event on the RX pin. If I only keep GND and Jetson TX → PC RX, I never receive the data on the PC.

  2. For the Jetson RX pin: when I type 123456789 in my PC terminal, I only receive some of the data: usually 459 for example.

If I loop back RX to TX on the jetson and send some text, I never receive it (nothing happens in the screen terminal).

Furthermore, I did not disable cboot uart logging, which means I receive debug data from Cboot when I start the Jetson NX on my PC terminal, and I can interrupt the boot sequence just fine by typing data. No character is lost in the process. It’s as if something was launched after the boot altering the ttyTHS2 port.

stty -a yields the same settings on ttyTHS1 and ttyTHS2

Any ideas? Thanks for your help!

Did you disable nvgetty.service? If not, then:

sudo systemctl stop nvgetty.service
sudo systemctl disable nvgetty.service

hello albanderuaz,

please see-also Topic 201881, it sometimes be an issue with the setup of serial port utility, please modify the settings for confirmation. thanks

Thanks for your reply!

nvgetty is indeed disabled. I tried with cutecom on PC and NX, the same problem appears.

I also tried on the latest L4T 32.7.1 today, same behaviour. UART console works fine during boot stage, stops after cboot as expected, then cutecom exhibits the same behaviour. I am using the developper kit carrier board.

If I do not perform the serial port modifications, communication on combined uart ttyTCU0 works correctly but I am getting spammed with kernel messages on the serial port.
Is disabling combined-uart in device tree and enabling serial@c280000 enough or am I missing another step?

hello albanderuaz,

there’re 3 UARTs available Jetson Xavier NX,
UART0 to M2
UART1 to 40PIN
UART2 to debug

could you please refer to Jetson Xavier NX Product Design Guide and share the hardware connections you’d done.


I connected my usb adapter RX to UART2_TXD pin 236, GND, and my usb adapter TX to UART2_RXD pin 238.
USB adapter is configured to work in 3.3V mode.


hello albanderuaz,

please check $ dmesg | grep THS for the register node of uartc: serial@c280000
you should look into pinmux cfg and device tree definition for the mappings.
for example,

pinmux.0x0c302010 = 0x00000400; # uart3_tx_pcc5: uartc,...
pinmux.0x0c302008 = 0x00000458; # uart3_rx_pcc6: uartc,...


        uartc: serial@c280000 {
                clocks = <&bpmp_clks TEGRA194_CLK_UARTC>,
                        <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;


The output is:

[    1.479934] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART
[    1.481002] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART
[    1.481698] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 49, base_baud = 0) is a TEGRA_UART

Device tree content:

serial@c280000 {
		compatible = "nvidia,tegra186-hsuart";
		iommus = <0x2 0x20>;
		reg = <0x0 0xc280000 0x0 0x10000>;
		reg-shift = <0x2>;
		interrupts = <0x0 0x72 0x4>;
		nvidia,memory-clients = <0xe>;
		dmas = <0x1b 0x3 0x1b 0x3>;
		dma-names = "rx", "tx";
		clocks = <0x4 0x9d 0x4 0x66>;
		clock-names = "serial", "parent";
		resets = <0x5 0x66>;
		reset-names = "serial";
		status = "okay";
		linux,phandle = <0xf1>;
		phandle = <0xf1>;

in aliases:
serial2 = "/serial@c280000";

in symbols:
uartc = "/serial@c280000";


pinmux.0x0c302010 = 0x00000400; # uart3_tx_pcc5: uartc, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302008 = 0x00000450; # uart3_rx_pcc6: uartc, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable

cutecom is performed on ttyTHS2.

Thanks for your help!

I ended up reenabling combined-uart and removing bpmp, cboot and kernel console, providing me with a clean uart after boot. If anyone knows how to bypass the use of combined uart to directly use ttyTHS2 instead, I’m interested!

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.