Hi,
Does the agx as root have it’s own on-module termination for the pcie clocks it provides to the endpoint connected to it?:
Regards,
Itai
The ref clk is from Jetson directly.
Hi,
So no need of HCSL termination on those signals?
Please refer to chapter PCIe Interface Signal Routing Requirements up to Gen4 in Design Guide for custom design.
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