I’m developing embedded firmware to manage the power sequencing for a Jetson AGX Orin SoM on a custom carrier board. For this, I’ve been following the Jetson AGX Orin Series Modules Design Guide (DG-10653-001_v1.7).
However, I’ve encountered inconsistencies between the design guide’s shutdown sequence description and the actual behavior of the SoM during shutdown.
To eliminate the possibility of errors in my hardware or firmware, I tested the same signals on an Orin development board (P3737_A05). When probing the relevant signals, I observed the following deviations from the design guide (refer to Figure 5-3 in section 5.1.2 of DG-10653-001_v1.7):
MODULE_SHUTDOWN_N does not behave as expected—it does not stay low during the shutdown process. Instead, it only shows a brief negative transient.
VDDIN_PWR_BAD_N does not de-assert (go low) at all.
The sequence of events differs: SYS_RESET_N goes low first, followed by CARRIER_POWER_ON, but MODULE_POWER_ON does not de-assert before CARRIER_POWER_ON, directly violating the note in Figure 5-3.
This discrepancy makes it unclear how to reliably detect a shutdown event. For example, the signals I rely on in my MCU firmware to detect a shutdown (which are driven by the SoM) do not toggle as expected.
Even the button-hold shutdown case exhibits similar behavior, so this isn’t limited to just one shutdown method. While some might argue that I should just adhere to the design guide regardless of the development board’s behavior, I believe this isn’t practical because my MCU’s firmware depends on the SoM signaling shutdown events correctly.
My question: How can I reliably detect a shutdown event for the Jetson AGX Orin, given this mismatch between the design guide and the observed behavior?
Hi, I am not sure how you did this test. In fact, MOD_SHUTDOWN_N is tied to VIN_PWR_BAD_N thru a gate in module. They both should be low at almost same time if MOD_SHUTDOWN_N is pulled low. Could you use a scope to trigger and capture timings at the main connector pins?
The scope capture above was captured using a saleae logic pro 8. I soldered 4 wires to the first 4 points listed below and attached my scope probes to those. Here are the points on P3737_A05 that I soldered to:
CARRIER_POWER_ON → TP74 3.3V
MOD_SHUTDOWN_N_3V3 → R952 - U102 3.3V
VIN_PWR_BAD_N → R887 - Q526 5.0V
MODULE_POWER_ON → R1119 - R1188 3.3V
SYS_RST_IN_N → J42-3 (No soldering) 1.8V
I would capture timings at the main connector if I can, but its very difficult to impossible to capture all those signals at the main connector on the development kit.
Thank you for your reply @Trumany. I have captured MOD_SHUTDOWN_N from the SoM at R1054 and it does toggle low indeed as mentioned in the design guide. It unfortunately toggles low at the same time as system reset. So it looks like monitoring that signal MOD_SHUTDOWN_N in addition to SYSTEM_RESET_N does not provide much value.
VIN_PWR_BAD_N however, still exhibits the same behavior.
This however, does not explain why this sequence is totally different from the one in the design guide for software shutdown!!!
When would we be able to get an updated design guide? In the meantime, could you provide guidance on the following:
What are all the possible power down sequences for the ORIN AGX?
What do these sequences look like?
What signals should the user monitor and what signals should the user control during these sequences? Most of the signals in question are bi-directional and it is impossible to discern which signals are to be monitored and which to be controlled from the existing design guide.
I would be happy to review any drafts and provide early feedback if you would like.
Thanks for your finding. As communicated earlier in earlier post here, confirming again that your sequence is correct. The SW shutdown sequence in current Design Guide needs to be updated and will be updated in next release.
