Jetson Orin Nano (8gb) cache-line size and page size

[cedricyangks]

Since the tegra23x is a SOC on the jetson orin nano, is the HOST (CPU) cache-line also 128 bit bus width?

Also what would be the default memory page size (4096 bytes)

From running devicequery samples it shows 128 bit bus width, is that applicable to the whole SOC or just igpu side?

Device 0: "Orin"
  CUDA Driver Version / Runtime Version          11.4 / 11.4
  CUDA Capability Major/Minor version number:    8.7
  Total amount of global memory:                 7471 MBytes (7834025984 bytes)
  (008) Multiprocessors, (128) CUDA Cores/MP:    1024 CUDA Cores
  GPU Max Clock rate:                            624 MHz (0.62 GHz)
  Memory Clock rate:                             624 Mhz
  Memory Bus Width:                              128-bit
  L2 Cache Size:                                 2097152 byt

[AastaLLL]

Hi,

Cache-line is a system-wide info.
Jetson is a shared memory system so the host cache-line is also 128-bit.

Page size is 4K.

Thanks.