Jetson Orin Nano | AON Cluster (SPE) | PWM Support

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin Nano
1

Hi,

I am using Jetson Orin Nano Developer Kit, Jetpack 6.2, L4T 36.4.3 and running FreeRTOS on the SPE.

I am referring to the SPE Developer guide.
It says PWM is a supported peripheral from the AON Cluster.

But the list of supported features by platform does not have PWM.
Does this mean that the SPE currently does not have the software support (PWM driver) or there is hardware limitation to have the support?

In the Orin TRM, I see that PWM4 is being used for the Fan control is always active via AON while the other PWM {1 - 3, 5 - 8} is not active on low power mode. It’s a bit confusing whether PWM controller instances {1 - 3, 5 - 8} can be used from the AON Cluster (after disabling them in the CCPLEX).

What is the PWM frequency range (minimum, maximum) that can be supported?

Any clarification would be nice.

Thanks,
Sundar

2

*** Please note that this reply is generated by LLM automatically ***

I’d be happy to help clarify the PWM support on the Jetson Orin Nano Developer Kit.

Firstly, the SPE Developer Guide mentions that PWM is a supported peripheral from the AON Cluster, but the list of supported features by platform does not have PWM. This implies that while the hardware supports PWM, the software support for PWM driver is not currently available on the SPE.

The Orin TRM (Technical Reference Manual) provides more insight into the PWM controller instances. It states that PWM4 is used for fan control and is always active via AON, while the other PWM instances (1, 3, 5, 8) are not active on low power mode. This suggests that PWM instances 1, 3, 5, 8 can be used from the AON Cluster after disabling them in the CCPLEX.

However, it’s essential to note that the PWM controller instances have specific frequency ranges. According to the Orin TRM, the PWM frequency range is programmable, with a maximum frequency of 48 MHz. The PWM controller can be programmed to divide the device clock by 256 before subdividing it based on a programmable value. The frequency division is a 13-bit programmable value, and pulse division is an 8-bit value.

To answer your question, the PWM frequency range that can be supported is from a minimum of (device clock frequency / 256) / 2^13 to a maximum of 48 MHz. However, the exact minimum frequency is not specified in the provided documentation.

In comparison, the Jetson Orin NX has four PWM outputs, each with a programmable frequency divider and pulse width generator. The PWM controller supports one PWM output for each of its four instances, with each instance allocated a 64 KB independent address space.

In summary, while the Jetson Orin Nano Developer Kit’s SPE does not currently have software support for PWM driver, the hardware supports PWM, and PWM instances 1, 3, 5, 8 can be used from the AON Cluster after disabling them in the CCPLEX. The PWM frequency range is programmable, with a maximum frequency of 48 MHz.

I hope this clarification helps, Sundar!

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4

Hello, sundar:
You are right.

  1. Only PWM4@0x0c340000 is within AON cluster.
  2. SPE is in AON cluster, and it has restrictions to access resources outside AON cluster.
  3. For the PWM clock, please take a look at Orin TRM. Corresponding chapter (PWM) provides some information from chip level. You can also take a look at the sys-FS nodes after Orin Nano boots up, to confirm the software side support.

br
ChenJian

5

Hi ChenJian,

Thank you for the response.

The IOMEM address range of all the PWM instances (0x0328_0000 - 0x032F_FFFF) seem to be in the neighbouring range as other peripherals such as SPI (0x0321_0000 - 0x0325_FFFF), I2C (0x0316_0000 - 0x031E_FFFF), UART (0x0310_0000 - 0x031D_FFFF), etc. I’d like to understand why the SPE have a limitation to use the other PWM instances {1-3, 5-8}?

Suppose, I disable all the PWM instances in Linux and use them from SPE with a custom PWM driver, would there be any issue from functionality perspective?

From low power mode operation standpoint, for those PWM instances that are not possible when used from SPE?
Can we restrict PWM instances from going to low power mode by keeping the PWM clock & power from getting gated?

Thanks,
Sundar

6

Hello, sundar:
The SPE R5 core is in AON cluster, and generally, only modules within AON cluster can be accessed with full function.
For the modules outside of AON cluster, some of them may be blocked and SPE R5 cannot access.
If PWM4@0x0c340000 is occupied by system with default fan, it cannot be used for other purpose.
For low power mode, do you mean SC7? In that mode, VDD_CORE and VDD_CPU are powered off. Most modules will not work. Modules inside AON cluster should still be powered. Frankly I’ve not checked whether there’s still output in PWM4 in SC7. It may depend on several logics from software.
SC7 is quite complicated. May I know more about your use case?

br
ChenJian

7

Hi ChenJian,

By low power mode, I mean when all the other clusters go into low power except the AON cluster.

I see that the peripherals on the APB are accessible via the AON cluster fabric from Cortex-R5 based on the below picture taken from the Orin TRM.

AON Cluster - PWM Controller
AON Cluster - PWM Controller977×730 176 KB

I am looking for the details on Clock and Power reset recipe for working with the PWM instances from SPE.

I want to know if the PWM instances won’t function at all when managed by the SPE or it’s just that they don’t operate when going into low power mode.

I’m looking to see how I can drive PWM instances from SPE (Cortex-R) for Drone flight control.

Thanks,
Sundar

8

Hello, sandar:
maybe my point is mis-understand, or I fail to understand your point.

  1. For PWM4@0x0c340000, it can be fully accessed by SPE, since it’s within AON cluster. Unfortunately, it’s occupied by system fan. Please do not mess up with low power mode (if that means SC7.) SC7 is another problem and it’s quite complicated. Clocks/powers are controlled by another processor (BPMP).
  2. For other PWM instances, which are outside AON cluster, SPE R5 cannot have full functional access. Since you’ve already noticed that block diagram, you can see that only 1 PWM instance inside AON with full connection to the bus.
  3. For your application, if fan is not needed, maybe you can try to disable that module in Linux side and access PWM4@0x0c340000 in SPE firmware. Anyway, it’s not an official feature, and it may need some coding efforts.

br
ChenJian

9

Hi ChenJian,

Thanks for the response.

Okay, I understand the limitations.
I’d like to try and use PWM3 instance from SPE. I can write my own custom driver.

I couldn’t find the CLK enable and reset register offsets in the CAR module for PWM3 in the SPE source though.
These are needed to be done prior to accessing the PWM3 registers to configure the parameters and use it.

Could you please share some information on the same? Please point me to a document that contains relevant details.

Thanks,
Sundar

10

Hello, sundar:

“I couldn’t find the CLK enable and reset register offsets in the CAR module for PWM3 in the SPE source though.
These are needed to be done prior to accessing the PWM3 registers to configure the parameters and use it.“

That’s another limitation for SPE access modules outside of AON cluster. That’s not recommended officially.

I can only provide some technical suggestions, and unfortunately, I have not tried these changes, and only for your reference. Also, I’m willing to share some thoughts, but cannot guarantee it can work.

  1. PWM3 is out of AON cluster, and you may have to investigate the feasibility for such implementation.
  2. For clock/reset, you can add a fake driver in CCPLEX (Linux) side for that.
  3. In SPE side, please try whether the registers are accessible after PWM3 clock is on.
  4. data_channel may help to communicate between CCPLEX and SPE to sync.

br

ChenJian

12

Hi ChenJian,

Okay, thank you for the possible approaches.

I’ll try your suggestions and see which one’s convenient.

Thanks,

Sundar

13

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