Hi,
We have developed a custom carrier that uses a TAS5720 digital amplifier for audio output and we can’t get it working.
The TAS5720 is connected to I2S2 and the datasheet specifies:
For the stereo formats (I2S, left-justified and right-justified), the TAS5720L/M device supports BCLK to LRCLK ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be tied directly to BCLK. Otherwise MCLK must be driven externally. The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of MCLK is 25MHz or less
We were expecting to set I2S2 (BCLK) to: 3072000Hz but pll_a and its child clocks don’t look ok.
Any ideas on what we are doing wrong?
Thx!
This is the dts:
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
#include "staging/tegra234-p3768-0000+p3767-0001.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
/ {
compatible = "nvidia,p3768-0000+p3767-0001", "nvidia,p3767-0001", "nvidia,tegra234";
model = "NVIDIA Jetson Orin NX SSI carrier";
sound {
assigned-clocks = <&bpmp TEGRA234_CLK_PLLA_OUT0>, <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA>, <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <0>, <12288000>;
nvidia-audio-card,widgets =
"Headphone", "TAS5720 Headphone";
nvidia-audio-card,routing =
"TAS5720 Headphone", "TAS5720 OUT";
i2s2_to_codec: nvidia-audio-card,dai-link@77 {
status = "okay";
link-name = "ssi-pi-audio-z-v2";
format = "i2s";
// link-type = <C2C_LINK>;
bit-format = "s32_le";
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "TAS5720";
i2s2_cpu: cpu {
sound-dai = <&tegra_i2s2 I2S_DAP>;
};
codec {
sound-dai = <&tas5720>;
prefix = "TAS5720";
};
};
};
bus@0 {
aconnect@2900000 {
ahub@2900800 {
i2s@2901100 {
clocks = <&bpmp TEGRA234_CLK_I2S2>,
<&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <3072000>;
status = "okay";
ports {
i2s2_port: port@1 {
reg = <1>;
i2s2_dap: endpoint {
dai-format = "i2s";
/* placeholder for external codec */
remote-endpoint = <&tas5720_ep>;
};
};
};
};
};
};
i2c@3160000 { //0 Light
status = "okay";
arb@73 {
compatible = "nxp,pca9641";
reg = <0x73>;
status = "okay";
i2c0_arb: i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
i2c1_lvds0_mux: mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c1_lvds0_mux_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
ina_leds_input: ina_leds_input@4b {
compatible = "ti,ina220";
reg = <0x4b>;
shunt-resistor = <4000>;
use-dt-name;
status = "okay";
};
ina_leds_r: ina_leds_r@48 {
compatible = "ti,ina220";
reg = <0x48>;
shunt-resistor = <4000>;
use-dt-name;
status = "okay";
};
ina_leds_ww: ina_leds_ww@46 {
compatible = "ti,ina220";
reg = <0x46>;
shunt-resistor = <100000>;
use-dt-name;
status = "okay";
};
ina_leds_cw: ina_leds_cw@42 {
compatible = "ti,ina220";
reg = <0x42>;
shunt-resistor = <100000>;
use-dt-name;
status = "okay";
};
};
i2c1_lvds0_mux_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
leds1_temp: leds1_temp@49 {
compatible = "national,lm75b";
reg = <0x49>;
use-dt-name;
status = "okay";
};
leds2_temp: leds2_temp@4a {
compatible = "national,lm75b";
reg = <0x4a>;
use-dt-name;
status = "okay";
};
tmp117@4b {
compatible = "ti,tmp116";
reg = <0x4b>;
};
};
i2c1_lvds0_mux_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c1_lvds0_mux_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c1_lvds0_mux_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
i2c1_lvds0_mux_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
i2c1_lvds0_mux_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
i2c1_lvds0_mux_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
};
};
};
i2c@c240000 { //1 sensor IR
status = "okay";
arb@75 {
compatible = "nxp,pca9641";
reg = <0x75>;
status = "okay";
i2c1_arb: i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
i2c@3180000 { //2
status = "okay";
i2c_mipi_csi0_mux: mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c_mipi_csi0_mux_0: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
ap1302: ap1302_mipi@3c {
compatible = "onnn,ap1302";
reg = <0x3c>;
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
standby-gpios = <&gpio TEGRA234_MAIN_GPIO(H, 6) GPIO_ACTIVE_LOW>;
status = "okay";
port {
ap1302_mipi_ep: endpoint {
remote-endpoint = <&mipi_csi1_ap_ep>;
link-frequencies =
/bits/ 64 <408000000>;
data-lanes = <1 2 3 4>;
};
};
sensors {
#address-cells = <1>;
#size-cells = <0>;
onnn,model = "onnn,ar1335";
sensor,model = "ar1335";
sensor,resolution = <3840 2160>;
sensor,format = <0x300a>; // MEDIA_BUS_FMT_SGRBG10_1X10
sensor@0 {
reg = <0>;
status = "okay";
sip = <0xf36c>;
};
};
};
};
i2c_mipi_csi0_mux_1: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c_mipi_csi0_mux_2: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
pwr_comms: pwr_comms@4f {
compatible = "ti,ina220";
reg = <0x4f>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
};
i2c_mipi_csi0_mux_3: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c_mipi_csi0_mux_4: i2c@4 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
tas5720: tas5720@6c {
#sound-dai-cells = <0>;
compatible = "ti,tas5720";
reg = <0x6c>;
status = "okay";
sound-name-prefix = "TAS5720";
port {
tas5720_ep: endpoint {
remote-endpoint = <&i2s2_dap>;
// mclk-fs = <256>;
link-name = "ssi-pi-audio-z-v2";
};
};
};
};
i2c_mipi_csi0_mux_5: i2c@5 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c_mipi_csi0_mux_6: i2c@6 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c_mipi_csi0_mux_7: i2c@7 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
i2c@c250000 { //7 perifs
status = "okay";
arb@72 {
compatible = "nxp,pca9641";
reg = <0x72>;
status = "okay";
i2c7_arb: i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
i2c1_mux: mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c1_mux_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c1_mux_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
cpu_5v: 5v_cpu@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
misc_3v3: 3v3_misc@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
aud_12v: 12v_audio@42 {
compatible = "ti,ina220";
reg = <0x42>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
exp_5v: 5v_exp@46 {
compatible = "ti,ina220";
reg = <0x46>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
npu_5v: 5v_npu@47 {
compatible = "ti,ina220";
reg = <0x47>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
cam_3v3: 3v3_camera@4a {
compatible = "ti,ina220";
reg = <0x4a>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
sign_3v3: 3v3_sign@4b {
compatible = "ti,ina220";
reg = <0x4b>;
shunt-resistor = <2000>;
use-dt-name;
status = "okay";
};
};
i2c1_mux_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
cpu_temp: cpu_temp@48 {
compatible = "national,lm75b";
reg = <0x48>;
use-dt-name;
status = "okay";
};
reg_temp: vreg_temp@49 {
compatible = "national,lm75b";
reg = <0x49>;
use-dt-name;
status = "okay";
};
};
i2c1_mux_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c1_mux_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
i2c100_mux: mux@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c100_mux_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c100_mux_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
micsgpio: pca9536@41 {
compatible = "nxp,pca9536";
reg = <0x41>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
i2c1_mux_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
i2c1_mux_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
i2c1_mux_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
};
};
};
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_csi1_ap_ep: endpoint@0 {
port-index = <0>;
bus-width = <4>;
remote-endpoint = <&ap1302_mipi_ep>;
};
};
};
};
};
};
};
};
clk_summary output:
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
sor_linka_input 0 0 0 0 0 0 50000 Y
i2s8_sync_input 0 0 0 0 0 0 50000 Y
i2s8_pad_m 0 0 0 0 0 0 50000 Y
i2s7_sync_input 0 0 0 0 0 0 50000 Y
i2s8_sync_clk 0 0 0 0 0 0 50000 Y
i2s7_pad_m 0 0 0 0 0 0 50000 Y
i2s7_sync_clk 0 0 0 0 0 0 50000 Y
emchub 0 0 0 467000390 0 0 50000 Y
mchub 0 0 0 233500195 0 0 50000 Y
mgbe3_eee_pcs 0 0 0 102000000 0 0 50000 Y
mgbe2_eee_pcs 0 0 0 102000000 0 0 50000 Y
mgbe1_eee_pcs 0 0 0 102000000 0 0 50000 Y
mgbe0_eee_pcs 0 0 0 102000000 0 0 50000 Y
mgbe3_rx_pcs_input 0 0 0 0 0 0 50000 Y
mgbe3_rx_pcs 0 0 0 0 0 0 50000 Y
mgbe3_rx_pcs_m 0 0 0 0 0 0 50000 Y
mgbe2_rx_pcs_input 0 0 0 0 0 0 50000 Y
mgbe2_rx_pcs 0 0 0 0 0 0 50000 Y
mgbe2_rx_pcs_m 0 0 0 0 0 0 50000 Y
mgbe1_rx_pcs_input 0 0 0 0 0 0 50000 Y
mgbe1_rx_pcs 0 0 0 0 0 0 50000 Y
mgbe1_rx_pcs_m 0 0 0 0 0 0 50000 Y
mgbe0_rx_pcs_input 0 0 0 0 0 0 50000 Y
mgbe0_rx_pcs 0 0 0 0 0 0 50000 Y
mgbe0_rx_pcs_m 0 0 0 0 0 0 50000 Y
fuse_burn 0 0 0 38400000 0 0 50000 Y
gpusysclk 1 1 0 306000000 0 0 50000 Y
mgbe3_rx_input 0 0 0 0 0 0 50000 Y
mgbe3_rx_input_m 0 0 0 0 0 0 50000 Y
mgbe2_rx_input 0 0 0 0 0 0 50000 Y
mgbe2_rx_input_m 0 0 0 0 0 0 50000 Y
mgbe1_rx_input 0 0 0 0 0 0 50000 Y
mgbe1_rx_input_m 0 0 0 0 0 0 50000 Y
mgbe0_rx_input 0 0 0 0 0 0 50000 Y
mgbe0_rx_input_m 0 0 0 0 0 0 50000 Y
pex1_c5_core 0 0 0 500000000 0 0 50000 Y
pex1_c5_core_m 0 0 0 500000000 0 0 50000 Y
pex0_c4_core 1 1 0 500000000 0 0 50000 Y
pex0_c4_core_m 0 0 0 500000000 0 0 50000 Y
pex0_c3_core 0 0 0 500000000 0 0 50000 Y
pex0_c3_core_m 0 0 0 500000000 0 0 50000 Y
pex0_c2_core 0 0 0 500000000 0 0 50000 Y
pex0_c2_core_m 0 0 0 500000000 0 0 50000 Y
pex0_c1_core 0 0 0 500000000 0 0 50000 Y
pex0_c1_core_m 0 0 0 500000000 0 0 50000 Y
pex0_c0_core 0 0 0 500000000 0 0 50000 Y
pex0_c0_core_m 0 0 0 500000000 0 0 50000 Y
pllp_out_jtag 0 0 0 51000000 0 0 50000 Y
pex2_c10_core 0 0 0 500000000 0 0 50000 Y
pex2_c10_core_m 0 0 0 500000000 0 0 50000 Y
dsi_pad_input 0 0 0 0 0 0 50000 Y
sor_pad_input 0 0 0 0 0 0 50000 Y
pre_sf0 0 0 0 0 0 0 50000 Y
pre_sor1 0 0 0 0 0 0 50000 Y
pre_sor0 0 0 0 0 0 0 50000 Y
pex2_c9_core 0 0 0 500000000 0 0 50000 Y
pex2_c9_core_m 0 0 0 500000000 0 0 50000 Y
pex2_c8_core 1 1 0 62500000 0 0 50000 Y
pex2_c8_core_m 0 0 0 62500000 0 0 50000 Y
pex2_c7_core 0 0 0 500000000 0 0 50000 Y
pex2_c7_core_m 0 0 0 500000000 0 0 50000 Y
pex1_c6_core 0 0 0 500000000 0 0 50000 Y
pex1_c6_core_m 0 0 0 500000000 0 0 50000 Y
pll_p 0 0 0 816000000 0 0 50000 Y
mphy_l1_rx_ana 0 0 0 583680000 0 0 50000 Y
mphy_l1_rx_ana_m 0 0 0 583680000 0 0 50000 Y
mphy_l0_rx_ana 0 0 0 583680000 0 0 50000 Y
mphy_l0_rx_ana_m 0 0 0 583680000 0 0 50000 Y
gpu_pwr 0 0 0 204000000 0 0 50000 Y
nafll_gpusys 0 0 0 765000000 0 0 50000 Y
nafll_gpc0 0 0 0 765000000 0 0 50000 Y
gpc0clk 1 1 0 306000000 0 0 50000 Y
fuse 0 0 0 38400000 0 0 50000 Y
pllrefe_vcoout 0 0 0 625000000 0 0 50000 Y
mgbe3_ptp_ref 0 0 0 312500000 0 0 50000 Y
mgbe2_ptp_ref 0 0 0 312500000 0 0 50000 Y
mgbe1_ptp_ref 0 0 0 312500000 0 0 50000 Y
mgbe0_ptp_ref 0 0 0 312500000 0 0 50000 Y
pllrefe_vcoout_gated 0 0 0 625000000 0 0 50000 Y
csite 0 0 0 625000000 0 0 50000 Y
mphy_l0_tx_ls_3xbit_div 0 0 0 26041666 0 0 50000 Y
mphy_l0_tx_ls_symb_div 0 0 0 434027 0 0 50000 Y
mphy_l0_tx_mux_symb_div 0 0 0 434027 0 0 50000 Y
mphy_l0_tx_2x_symb 0 0 0 434027 0 0 50000 Y
mphy_l0_tx_pre_symb 0 0 0 217013 0 0 50000 Y
mphy_l0_tx_symb 0 0 0 217013 0 0 50000 Y
mphy_l0_tx_symb_m 0 0 0 217013 0 0 50000 Y
mphy_l0_tx_ls_3xbit 0 0 0 26041666 0 0 50000 Y
mphy_l0_rx_hs_symb_div 0 0 0 625000000 0 0 50000 Y
mphy_l0_rx_ls_bit_div 0 0 0 12019230 0 0 50000 Y
mphy_l0_rx_ls_symb_div 0 0 0 600961 0 0 50000 Y
mphy_l0_rx_mux_symb_div 0 0 0 600961 0 0 50000 Y
mphy_l0_rx_symb 0 0 0 600961 0 0 50000 Y
mphy_l0_rx_symb_m 0 0 0 600961 0 0 50000 Y
mphy_l0_rx_ls_bit 0 0 0 12019230 0 0 50000 Y
mphy_core_pll_fixed 0 0 0 208333333 0 0 50000 Y
eqos_tx_divider 0 0 0 125000000 0 0 50000 Y
eqos_macsec_tx 0 0 0 125000000 0 0 50000 Y
eqos_tx 0 0 0 125000000 0 0 50000 Y
eqos_ptp_ref 0 0 0 25000000 0 0 50000 Y
eqos_axi 0 0 0 125000000 0 0 50000 Y
emc 1 1 0 204000000 0 0 50000 Y
eqos_rx_input 0 0 0 0 0 0 50000 Y
eqos_macsec_rx 0 0 0 0 0 0 50000 Y
eqos_rx 0 0 0 0 0 0 50000 Y
eqos_rx_m 0 0 0 0 0 0 50000 Y
pllp_div17 0 0 0 24000000 0 0 50000 Y
sor_safe 0 0 0 24000000 0 0 50000 Y
dpaux 0 0 0 24000000 0 0 50000 Y
i2s6_sync_input 0 0 0 0 0 0 50000 Y
i2s5_sync_input 0 0 0 0 0 0 50000 Y
i2s4_sync_input 0 0 0 24576000 0 0 50000 Y
i2s3_sync_input 0 0 0 0 0 0 50000 Y
i2s2_sync_input 0 0 0 15728640 0 0 50000 Y
i2s1_sync_input 0 0 0 0 0 0 50000 Y
i2s6_sync_clk 0 0 0 0 0 0 50000 Y
i2s5_sync_clk 0 0 0 0 0 0 50000 Y
i2s4_sync_clk 0 0 0 0 0 0 50000 Y
i2s3_sync_clk 0 0 0 0 0 0 50000 Y
i2s2_sync_clk 0 0 0 0 0 0 50000 Y
i2s1_sync_clk 0 0 0 0 0 0 50000 Y
dspk2_sync_clk 0 0 0 0 0 0 50000 Y
dspk1_sync_clk 0 0 0 0 0 0 50000 Y
dmic4_sync_clk 0 0 0 0 0 0 50000 Y
dmic3_sync_clk 0 0 0 0 0 0 50000 Y
dmic2_sync_clk 0 0 0 0 0 0 50000 Y
dmic1_sync_clk 0 0 0 0 0 0 50000 Y
osc 3 3 0 38400000 0 0 50000 Y
pll_hub 0 0 0 467000390 0 0 50000 Y
sor_linka_afifo 0 0 0 38400000 0 0 50000 Y
sor_linka_afifo_m 0 0 0 38400000 0 0 50000 Y
dsi_core 0 0 0 38400000 0 0 50000 Y
rg1 0 0 0 38400000 0 0 50000 Y
rg1_m 0 0 0 38400000 0 0 50000 Y
rg0 0 0 0 38400000 0 0 50000 Y
rg0_m 0 0 0 38400000 0 0 50000 Y
sppll1_vco 0 0 0 2700000000 0 0 50000 Y
sppll1_div27pn 0 0 0 100000000 0 0 50000 Y
sppll1_clkoutpn 0 0 0 270000000 0 0 50000 Y
nafll_cluster1_dsu 0 0 0 115200000 0 0 50000 Y
nafll_cluster0_dsu 0 0 0 115200000 0 0 50000 Y
nafll_dce 0 0 0 281600000 0 0 50000 Y
dce_cpu_nic 0 0 0 281600000 0 0 50000 Y
dce_cpu 0 0 0 281600000 0 0 50000 Y
dce_nic 0 0 0 281600000 0 0 50000 Y
nafll_ofa 0 0 0 780800000 0 0 50000 Y
ofa 0 0 0 780800000 0 0 50000 Y
nafll_seu1 0 0 0 473600000 0 0 50000 Y
fr_seu1 0 0 0 473600000 0 0 50000 Y
seu1 0 0 0 473600000 0 0 50000 Y
pll_gbe 0 0 0 100000000 0 0 50000 Y
uphy_gbe_pll2_tx_ref 0 0 0 500000000 0 0 50000 Y
mgbe3_tx 0 0 0 500000000 0 0 50000 Y
mgbe2_tx 0 0 0 500000000 0 0 50000 Y
mgbe1_tx 0 0 0 500000000 0 0 50000 Y
mgbe0_tx 0 0 0 500000000 0 0 50000 Y
uphy_gbe_pll2_xdig 0 0 0 312500000 0 0 50000 Y
mgbe3_mac_divider 0 0 0 312500000 0 0 50000 Y
mgbe3_macsec 0 0 0 312500000 0 0 50000 Y
mgbe3_mac 0 0 0 312500000 0 0 50000 Y
mgbe2_mac_divider 0 0 0 312500000 0 0 50000 Y
mgbe2_macsec 0 0 0 312500000 0 0 50000 Y
mgbe2_mac 0 0 0 312500000 0 0 50000 Y
mgbe1_mac_divider 0 0 0 312500000 0 0 50000 Y
mgbe1_macsec 0 0 0 312500000 0 0 50000 Y
mgbe1_mac 0 0 0 312500000 0 0 50000 Y
mgbe0_mac_divider 0 0 0 312500000 0 0 50000 Y
mgbe0_macsec 0 0 0 312500000 0 0 50000 Y
mgbe0_mac 0 0 0 312500000 0 0 50000 Y
mgbe3_tx_pcs 0 0 0 156250000 0 0 50000 Y
mgbe2_tx_pcs 0 0 0 156250000 0 0 50000 Y
mgbe1_tx_pcs 0 0 0 156250000 0 0 50000 Y
mgbe0_tx_pcs 0 0 0 156250000 0 0 50000 Y
pllgbe_hps 0 0 0 100000000 0 0 50000 Y
aon_uart_fst_mipi_cal 0 0 0 38400000 0 0 50000 Y
nafll_cluster1_core 0 0 0 1984000000 0 0 50000 Y
nafll_cluster0_core 0 0 0 1984000000 0 0 50000 Y
pll_nvhs 0 0 0 100000000 0 0 50000 Y
pllnvhs_hps 0 0 0 100000000 0 0 50000 Y
nafll_pva_vps 0 0 0 1190400000 0 0 50000 Y
pva0_vps 0 0 0 115200000 0 0 50000 Y
nafll_pva_core 0 0 0 857600000 0 0 50000 Y
pva0_cpu_axi 0 0 0 115200000 0 0 50000 Y
nafll_bpmp 0 0 0 204800000 0 0 50000 Y
sf1 0 0 0 38400000 0 0 50000 Y
sf0 0 0 0 38400000 0 0 50000 Y
dsi_pixel 0 0 0 38400000 0 0 50000 Y
sor1 0 0 0 38400000 0 0 50000 Y
sor1_m 0 0 0 38400000 0 0 50000 Y
sor0 0 0 0 38400000 0 0 50000 Y
sor0_m 0 0 0 38400000 0 0 50000 Y
nafll_dla0_core 0 0 0 614400000 0 0 50000 Y
dla0_core 0 0 0 614400000 0 0 50000 Y
nafll_dla0_falcon 0 0 0 294400000 0 0 50000 Y
dla0_falcon 0 0 0 294400000 0 0 50000 Y
nafll_vic 0 0 0 729600000 0 0 50000 Y
vic 0 0 0 729600000 0 0 50000 Y
nafll_vi 0 0 0 832000000 0 0 50000 Y
vi 0 0 0 832000000 0 0 50000 Y
usb2_trk 0 0 0 9600000 0 0 50000 Y
uartc 0 0 0 1828571 0 0 50000 Y
nafll_tsec 0 0 0 960000000 0 0 50000 Y
tsec 0 0 0 960000000 0 0 50000 Y
mphy_flsm 0 0 0 38400000 0 0 50000 Y
dmic5 0 0 0 298832 0 0 50000 Y
sor1_ref 0 0 0 38400000 0 0 50000 Y
sor0_ref 0 0 0 38400000 0 0 50000 Y
nafll_se 0 0 0 473600000 0 0 50000 Y
fr_se 0 0 0 473600000 0 0 50000 Y
se 0 0 0 473600000 0 0 50000 Y
pll_c4 0 0 0 672000000 0 0 50000 Y
pllc4_vco_div2 0 0 0 336000000 0 0 50000 Y
pllc4_out2 0 0 0 134400000 0 0 50000 Y
pllc4_out1 0 0 0 224000000 0 0 50000 Y
pllc4_muxed 0 0 0 224000000 0 0 50000 Y
nafll_sce 0 0 0 281600000 0 0 50000 Y
sce_cpu_nic 0 0 0 281600000 0 0 50000 Y
sce_cpu 0 0 0 281600000 0 0 50000 Y
sce_nic 0 0 0 281600000 0 0 50000 Y
nafll_rce 1 1 0 614400000 0 0 50000 Y
rce_cpu_nic 3 3 0 115200000 0 0 50000 Y
rce_cpu 1 1 0 115200000 0 0 50000 Y
rce_nic 1 1 0 115200000 0 0 50000 Y
aon_touch 0 0 0 38400000 0 0 50000 Y
nafll_nvjpg 0 0 0 729600000 0 0 50000 Y
nvjpg 0 0 0 729600000 0 0 50000 Y
nafll_nvenc 0 0 0 793600000 0 0 50000 Y
nvenc 0 0 0 793600000 0 0 50000 Y
vpll1 0 0 0 270000000 0 0 50000 Y
nvdisplay_p1 0 0 0 270000000 0 0 50000 Y
vpll0_ref 0 0 0 38400000 0 0 50000 Y
vpll0 0 0 0 270000000 0 0 50000 Y
nvdisplay_p0_ref 0 0 0 270000000 0 0 50000 Y
sor1_pll_ref 0 0 0 270000000 0 0 50000 Y
pre_sor1_ref 0 0 0 270000000 0 0 50000 Y
sor0_pll_ref 0 0 0 270000000 0 0 50000 Y
sor0_div 0 0 0 270000000 0 0 50000 Y
pre_sor0_ref 0 0 0 270000000 0 0 50000 Y
nvdisplay_p0 0 0 0 270000000 0 0 50000 Y
dsipll_vco 0 0 0 1350000000 0 0 50000 Y
dsipll_clkoutpn 0 0 0 135000000 0 0 50000 Y
dsipll_clkouta 0 0 0 337500000 0 0 50000 Y
disppll 0 0 0 1080000000 0 0 50000 Y
disp 0 0 0 1080000000 0 0 50000 Y
dsc 0 0 0 360000000 0 0 50000 Y
disphubpll 0 0 0 12698437 0 0 50000 Y
nafll_nvdec 0 0 0 857600000 0 0 50000 Y
nvdec 0 0 0 857600000 0 0 50000 Y
pll_nvcsi 0 0 0 1285800000 0 0 50000 Y
nvcsi 0 0 0 642900000 0 0 50000 Y
mphy_tx_1mhz_ref 0 0 0 1010526 0 0 50000 Y
pll_e 0 0 0 100000000 0 0 50000 Y
plle_hps 0 0 0 100000000 0 0 50000 Y
uphy_pll3 0 0 0 500000000 0 0 50000 Y
mphy_l0_tx_hs_symb_div 0 0 0 500000000 0 0 50000 Y
sppll0_vco 1 1 0 2700000000 0 0 50000 Y
sppll0_div27pn 0 0 0 100000000 0 0 50000 Y
sppll0_div25 1 1 0 108000000 0 0 50000 Y
aza_2xbit 2 2 0 108000000 0 0 50000 Y
aza_bit 1 1 0 54000000 0 0 50000 Y
sppll0_clkoutpn 0 0 0 270000000 0 0 50000 Y
dp_link_ref 0 0 0 270000000 0 0 50000 Y
sppll0_clkouta 0 0 0 900000000 0 0 50000 Y
sppll0_clkoutb 0 0 0 540000000 0 0 50000 Y
hub 0 0 0 540000000 0 0 50000 Y
sppll0_div10 0 0 0 270000000 0 0 50000 Y
maud 0 0 0 270000000 0 0 50000 Y
nafll_isp 0 0 0 1011200000 0 0 50000 Y
isp 0 0 0 1011200000 0 0 50000 Y
utmip_pll 0 0 0 960000000 0 0 50000 Y
utmipll_clkout48 0 0 0 48000000 0 0 50000 Y
xusb_fs 0 0 0 48000000 0 0 50000 Y
xusb_fs_dev 0 0 0 48000000 0 0 50000 Y
xusb_fs_host 0 0 0 48000000 0 0 50000 Y
utmipll_clkout480 0 0 0 480000000 0 0 50000 Y
mgbes_app 0 0 0 480000000 0 0 50000 Y
mgbe3_app 0 0 0 480000000 0 0 50000 Y
mgbe2_app 0 0 0 480000000 0 0 50000 Y
mgbe1_app 0 0 0 480000000 0 0 50000 Y
mgbe0_app 0 0 0 480000000 0 0 50000 Y
xusb_ss 0 0 0 120000000 0 0 50000 Y
xusb_ss_superspeed 0 0 0 120000000 0 0 50000 Y
xusb_ss_dev 0 0 0 120000000 0 0 50000 Y
xusb_hs_hsicp 0 0 0 120000000 0 0 50000 Y
nafll_nvjpg1 0 0 0 729600000 0 0 50000 Y
nvjpg1 0 0 0 729600000 0 0 50000 Y
pll_aon 1 1 0 400000000 0 0 50000 Y
can2 0 0 0 200000000 0 0 50000 Y
can2_core 0 0 0 200000000 0 0 50000 Y
can2_host 0 0 0 200000000 0 0 50000 Y
can1 3 3 0 200000000 0 0 50000 Y
can1_core 1 1 0 50000000 0 0 50000 Y
can1_host 1 1 0 200000000 0 0 50000 Y
pll_c 0 0 0 199999804 0 0 50000 Y
qspi1_2x_pm 0 0 0 199999804 0 0 50000 Y
qspi1_pm 0 0 0 199999804 0 0 50000 Y
qspi0_2x_pm 0 0 0 199999804 0 0 50000 Y
qspi0_pm 0 0 0 99999902 0 0 50000 Y
pll_c2 0 0 0 204000000 0 0 50000 Y
axi_cbb 0 0 0 204000000 0 0 50000 Y
apb2ape 0 0 0 204000000 0 0 50000 Y
pll_a 0 0 0 294911718 0 0 50000 Y
plla_out0 0 0 0 49151953 0 0 50000 Y
i2s8 0 0 0 12287989 0 0 50000 Y
i2s7 0 0 0 12287989 0 0 50000 Y
i2s6 0 0 0 49151953 0 0 50000 Y
i2s5 0 0 0 1535998 0 0 50000 Y
i2s4 0 0 0 24575976 0 0 50000 Y
i2s3 0 0 0 1535998 0 0 50000 Y
i2s2 0 0 0 16383984 0 0 50000 Y
i2s1 0 0 0 49151953 0 0 50000 Y
dspk2 0 0 0 7021707 0 0 50000 Y
dspk1 0 0 0 7021707 0 0 50000 Y
dmic4 0 0 0 3071997 0 0 50000 Y
dmic3 0 0 0 7021707 0 0 50000 Y
dmic2 0 0 0 3071997 0 0 50000 Y
dmic1 0 0 0 3071997 0 0 50000 Y
aud_mclk 0 0 0 7021707 0 0 50000 Y
pll_a1 0 0 0 699999609 0 0 50000 Y
plla1_out1 0 0 0 174999902 0 0 50000 Y
ape 0 0 0 174999902 0 0 50000 Y
aclk 0 0 0 699999609 0 0 50000 Y
adsp 0 0 0 699999609 0 0 50000 Y
adspneon 0 0 0 699999609 0 0 50000 Y
clk_m 2 2 0 19200000 0 0 50000 Y
tach1 0 0 0 3200000 0 0 50000 Y
sdmmc4_axicif 0 0 0 19200000 0 0 50000 Y
la 0 0 0 19200000 0 0 50000 Y
fuse_serial 0 0 0 19200000 0 0 50000 Y
ist 0 0 0 19200000 0 0 50000 Y
ufsdev_ref 0 0 0 19200000 0 0 50000 Y
tach0 1 1 0 1010526 0 0 50000 Y
sdmmc4 0 0 0 19200000 0 0 50000 Y
pwm8 0 0 0 19200000 0 0 50000 Y
pwm2 0 0 0 19200000 0 0 50000 Y
actmon 1 1 0 19200000 0 0 50000 Y
clk_32k 1 1 0 32768 0 0 50000 Y
i2c_slow 0 0 0 32768 0 0 50000 Y
aon_i2c_slow 0 0 0 32768 0 0 50000 Y
pllp_out0 5 10 0 408000000 0 0 50000 Y
pwm3 1 1 0 11027028 0 0 50000 Y
dsi_lp 0 0 0 204000000 0 0 50000 Y
nvhs_pll1_mgmt 0 0 0 102000000 0 0 50000 Y
gbe_pll2_mgmt 0 0 0 102000000 0 0 50000 Y
gbe_pll1_mgmt 0 0 0 102000000 0 0 50000 Y
gbe_pll0_mgmt 0 0 0 102000000 0 0 50000 Y
gbe_rx_byp_ref 0 0 0 204000000 0 0 50000 Y
spi5 0 0 0 81600000 0 0 50000 Y
spi4 0 0 0 81600000 0 0 50000 Y
xusb_falcon 0 0 0 408000000 0 0 50000 Y
xusb_falcon_ss 0 0 0 408000000 0 0 50000 Y
xusb_falcon_host 0 0 0 408000000 0 0 50000 Y
xusb_core_mux 0 0 0 102000000 0 0 50000 Y
xusb_core_ss 0 0 0 102000000 0 0 50000 Y
xusb_core_host 0 0 0 102000000 0 0 50000 Y
xusb_core_dev 0 0 0 102000000 0 0 50000 Y
nvhs_pll0_mgmt 0 0 0 102000000 0 0 50000 Y
nvhs_rx_byp_ref 0 0 0 204000000 0 0 50000 Y
pex_usb_pad_pll3_mgmt 0 0 0 102000000 0 0 50000 Y
pex_usb_pad_pll2_mgmt 0 0 0 102000000 0 0 50000 Y
pex_usb_pad_pll1_mgmt 0 0 0 102000000 0 0 50000 Y
pex_usb_pad_pll0_mgmt 0 0 0 102000000 0 0 50000 Y
pex_sata_usb_rx_byp 0 0 0 204000000 0 0 50000 Y
sdmmc_legacy_tm 0 0 0 12000000 0 0 50000 Y
dbgapb 0 0 0 136000000 0 0 50000 Y
vi_const 0 0 0 408000000 0 0 50000 Y
uarth 0 0 0 68000000 0 0 50000 Y
uartj 0 0 0 1837837 0 0 50000 Y
uarti 0 0 0 1837837 0 0 50000 Y
ufshc 0 0 0 204000000 0 0 50000 Y
uartf 0 0 0 68000000 0 0 50000 Y
uarte 0 0 0 68000000 0 0 50000 Y
uartd 0 0 0 68000000 0 0 50000 Y
uartb 0 0 0 68000000 0 0 50000 Y
uarta 0 0 0 68000000 0 0 50000 Y
tsec_pka 0 0 0 204000000 0 0 50000 Y
spi3 0 0 0 81600000 0 0 50000 Y
spi2 0 0 0 81600000 0 0 50000 Y
spi1 0 0 0 81600000 0 0 50000 Y
sdmmc1 0 0 0 204000000 0 0 50000 Y
pwm7 1 1 0 408000000 0 0 50000 Y
pwm6 0 0 0 204000000 0 0 50000 Y
pwm5 1 1 0 408000000 0 0 50000 Y
pwm4 0 0 0 204000000 0 0 50000 Y
pwm1 1 1 0 408000000 0 0 50000 Y
nvcsilp 0 0 0 408000000 0 0 50000 Y
uart_fst_mipi_cal 0 0 0 102000000 0 0 50000 Y
mipi_cal 0 0 0 102000000 0 0 50000 Y
i2c9 0 0 0 204000000 0 0 50000 Y
i2c8 0 1 0 136000000 0 0 50000 Y
i2c7 0 0 0 204000000 0 0 50000 Y
i2c6 0 1 0 136000000 0 0 50000 Y
i2c4 0 0 0 204000000 0 0 50000 Y
i2c3 0 1 0 136000000 0 0 50000 Y
i2c2 0 1 0 136000000 0 0 50000 Y
i2c1 0 1 0 136000000 0 0 50000 Y
host1x 1 1 0 204000000 0 0 50000 Y
extperiph4 0 0 0 51000000 0 0 50000 Y
extperiph3 0 0 0 51000000 0 0 50000 Y
extperiph2 0 0 0 51000000 0 0 50000 Y
extperiph1 0 0 0 51000000 0 0 50000 Y
aon_cpu_nic 0 0 0 204000000 0 0 50000 Y
aon_nic 0 0 0 204000000 0 0 50000 Y
aon_apb 0 0 0 204000000 0 0 50000 Y
mss_encrypt 0 0 0 40800000 0 0 50000 Y
ahub 0 0 0 81600000 0 0 50000 Y
custom_carrier.dts.txt (18.5 KB)
dmesg.txt (59.0 KB)
clk_summary.txt (41.6 KB)