Jetson Thor interrupt nvvrs-pseq-irq interrupt trigger issue

[xus]

We are encountering a persistent nvvrs-pseq-irqinterrupt trigger on our Jetson Thor T5000-based motherboard after system boot. Comparative analysis with the devkit reveals that the NVVRS_PSEQ_REG_CTL_STATregister value is 0x1Fin our configuration (with interrupts triggered), while it is 0x3Fin the devkit (with no interrupts). Cross-validation tests confirm:

1. Our motherboard + devkit core + devkit SSD → 0x3F(no interrupts).

2. Devkit motherboard + our core + our SSD → 0x3F(no interrupts).

   The interrupt only triggers when NVVRS_PSEQ_REG_CTL_STAT = 0x1F. We seek clarification on:

   • The definition of BIT5in NVVRS_PSEQ_REG_CTL_STAT.

   • Potential factors causing this bit to change.

[WayneWWW]

Hi,

I just wonder what is “our core” there.

Could you dump SOM EERPOM content for us to check?

I think the comparison here should be devkit core on your board and devkit core on devkit.

[xus]

0x50_failed.txt (1.3 yes, KB)

Core refers to SOM. Devkit Core denotes the SOM disassembled from the devkit. The attached is EEPROM content extracted from our SOM.

[WayneWWW]

Hi,

I know what you are trying to say with Devkit core.

My point was there should be no difference between “devkit core” and “your core”. You should just use one core to compare between your board and devkit.

So please clarify whether this issue happen to only your carrier board or even devkit.