I am going to connect a CSI-2 4 lane camera to the Jetson-TK1. But I’m not sure which camera data-lane should connect to which pin of Tegra K1.
Is there any constraint for CSI-2 pin assignment on Jetson-TK1? Or is the pin assignment configurable?
The CSI-2 camera has 4 data lanes and 1 clock lane as data0, data1, data2, data3, clk.
The following pins can be used for CSI-2 camera.
J3A2 connector Camera port
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CSI_A_D0_P/N --> for data0?
CSI_A_D1_P/N --> for data1?
CSI_A_CLK_P/N --> for clk?
CSI_B_D0_P/N --> for data2?
CSI_B_D1_P/N --> for data3?
Anyway, let me ask again about CSI-2 data lane configuration.
The signal names, described in two documents “schematic of Jetson-TK1” and “Technical Reference Manual (TRM)”, do not match.
In the schematic the following signals are defined:
CSI_A_D0_N/P
CSI_A_D1_N/P
CSI_A_CLK_N/P
CSI_B_D0_N/P
CSI_B_D1_N/P
CSI_E_D0_N/P
CSI_E_CLK_N/P
The CSI_A_D[1:0] and CSI_B_D[1:0] could be a 4-Lane data signals, I think.
TRM describes, however,
Camera A is assigned to DSI & CSI x4 Pins (shared)
Camera B is assigned to CSI x4 Pins
Camera C is assigned to CSI x1 Pins
I think that “Camera B” might be CSI_A_D[1:0] and CSI_B_D[1:0], and “Camera C” might be CSI_E_D0.
Is my understanding correct?
And… How do I configure data lane of CSI-2 4-lane for Jetson TK1 connector?
Your assumption that CSI_A_D[1:0] and CSI_B_D[1:0] are the 4-Lane data signals sounds very reasonable, but I would prefer verifying it somewhere before making a headboard.
Maybe you already had success and could share some of your insight.
CSI_E_D0_N/P & CSI_E_CLK_N/P on J3A2 is for additional 1 data lane Camera C connection.
Jetson TK1 board does not support connecting 4 data lanes Camera A since the following ball names are not connected with any of expansion I/O connectors in the schematic.
There’s no TP(Test Point) available for direct wiring from the board either.