Jetson TK1 DDR3 DQ Mapping

I am looking at the schematics for the Jetson TK1 DDR3L Memory interface with the 4 x16 parts. The DQ mapping seems odd to me. Ex. byte lane 3 DQ0 of U4B1 is mapped to DDR_DQ<24> that then goes to DDR_DQ17 of the TK1 memory controller, I would have assume it would be DDR_DQ16 being the LSB. Same byte lane and DQ4 is mapped to DDR_DQ<29> that then goes to DDR_DQ22, would assumed it would have been DDR_DQ20

I have looked over the memory controller specification in the datasheet but cannot seem to find anything on this mapping.

I am curious why this mapping is the case.

I just answered my own question. The TK1 has pin multiplexing on the memory controller to make layout easier. Very nice. I like the option. It is using Option #14

Yes, The byte and data bit signal within byte group(DQ/DM/DQS) can be swapped for layout easier.
The interface design guide have the description.
The schematic also modified some DDR signal name on TK1 symbol which is different with ball name of datasheet.