[Jetson TK1] DSI_B_D use as CSI problem

Hi.

I develop CSI-2 stereo camera on Tegra K1 custom board.

Our hardware use below CSI-2 lane for using x4 lane.

camera1 : CSI_A_D[1:0]_N/P, CSI_B_D[1:0]_N/P ,CSI_A_CLK_N/P 
camera2 : DSI_B_CLK_N/P , DSI_B_D[3:0]_N/P

I develop v4l2 driver refer to imx135_v4l2.c.
And I developed camera1 successfully.
Below command is to stream camera1.

gst-launch-1.0 v4l2src device="/dev/video0" ! 'video/x-bayer,format=bggr,width=1280,height=720' ! bayer2rgb ! videoconvert ! xvimagesink sync=false

But I can’t see camera2 stream to use same driver.

  • Below is my work code for camera2.
    1. Change Pad Control.
    2. arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi
      mipi_pad_ctrl_dsi_b {                                                                                       
                      nvidia,pins = "mipi_pad_ctrl_dsi_b";                                                                                       
                      <s>nvidia,function = "dsi_b";</s>                                                                                
                      nvidia,function = "csi";
                  };
      
    3. Add platform_device to "arch/arm/mach-tegra/board-ardbeg-sensors.c" same as camera1. Below is my added code.
    4. static struct tegra_io_dpd csic_io = {
          .name           = "DSI",
          .io_dpd_reg_index   = 0, 
          .io_dpd_bit     = 2, 
      };
      
      static struct tegra_io_dpd csid_io = {
          .name           = "DISB",
          .io_dpd_reg_index   = 1, 
          .io_dpd_bit     = 7, 
      };
      
      // Same code at v4l2 driver .s_power
      static int ardbeg_ap0101_power(struct device *dev, int enable)
      {   
          if(enable) {    
              tegra_io_dpd_disable(&csic_io); // Is it correct to use CSI_C??
              tegra_io_dpd_disable(&csid_io); // Is it correct to use CSI_D??
          } else {
              tegra_io_dpd_enable(&csic_io);
              tegra_io_dpd_enable(&csid_io);
          }
          
          return 0; 
      }   
      
      static struct i2c_board_info ardbeg_ap0101_camera_i2c_device_1 = {
          I2C_BOARD_INFO("ap0101at", 0x72),
          .platform_data = &ardbeg_ap0101_data,
      };
      
      static struct tegra_camera_platform_data ardbeg_ap0101_camera_platform_data_1 = {
          .flip_v         = 0,
          .flip_h         = 0,
          .port           = TEGRA_CAMERA_PORT_CSI_B,
          .lanes          = 4,
          .continuous_clk     = 1,
      };
      
      static struct soc_camera_link ap0101_iclink_1 = {
          .bus_id     = 1, /* This must match the .id of tegra_vi01_device */
          .board_info = &ardbeg_ap0101_camera_i2c_device_1,
          .module_name    = "ap0101at",
          .i2c_adapter_id = 0,
          .power      = ardbeg_ap0101_power,
          .priv       = &ardbeg_ap0101_camera_platform_data_1,
      };
      
      static struct platform_device ardbeg_ap0101_soc_camera_device_1 = {
          .name   = "soc-camera-pdrv",
          .id = 2,
          .dev    = {
              .platform_data = &ap0101_iclink_1,
          },
      };
      
    5. gst-launch output.
    6. [   76.684125] MIPI calibration for CSI is done
      [   76.887753] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 1, err = -11
      [   76.900737] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   76.905679] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   76.915782] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   76.925924] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   76.937733] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   76.944773] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   76.952677] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   76.962827] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   76.974731] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   76.981439] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   76.987117] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   76.992079] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   77.056709] ap0101at_set_output:1038] success!!! output enable change config
      [   77.068738] ap0101at_s_stream:1252] success to set up output enable!!!
      [   77.125469] ap0101at 0-0072: ap0101at_s_stream:1258] OUT-----
      [   77.196959] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 2, err = -11
      [   77.205098] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   77.210501] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   77.215712] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   77.220547] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   77.225365] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   77.231069] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   77.235976] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   77.240917] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   77.245736] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   77.251473] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   77.257172] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   77.262107] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   77.466939] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 3, err = -11
      [   77.475057] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   77.480250] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   77.485149] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   77.489885] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   77.494774] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   77.499678] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   77.504551] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   77.509360] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   77.514282] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   77.519871] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   77.525649] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   77.530586] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   77.734982] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 4, err = -11
      [   77.742853] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   77.748163] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   77.753036] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   77.757777] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   77.762591] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   77.767653] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   77.772473] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   77.777293] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   77.782173] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   77.787889] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   77.793641] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   77.798536] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   78.002923] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 5, err = -11
      [   78.010008] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   78.014783] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   78.019664] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   78.024468] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   78.029300] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   78.034033] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   78.039083] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   78.043900] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   78.048806] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   78.054463] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   78.060156] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   78.065206] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   78.269841] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 6, err = -11
      [   78.279323] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   78.286739] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   78.292586] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   78.297754] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   78.303120] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   78.309292] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   78.316386] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   78.321514] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   78.326431] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   78.332365] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   78.338156] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   78.344269] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   78.550850] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 7, err = -11
      [   78.558905] TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
      [   78.564471] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
      [   78.570273] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
      [   78.575419] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
      [   78.580871] TEGRA_CSI_CSI_CILB_STATUS 0x00000000
      [   78.585616] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
      [   78.590460] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
      [   78.595345] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
      [   78.600382] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
      [   78.606238] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
      [   78.611851] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
      [   78.616912] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
      [   78.822007] vi vi.1: CSI_B/CSI_C syncpt timeout, syncpt = 8, err = -11
      ....
      
  • Question.
    1. Is is correct way? To use CSI_C/D_D(DSI_B_D[3:0]) set csic_io, csid_io I necessarily use DSIB(APBDEV_PMC_IO_DPD2_REQ_0:7bit) and DSI(APBDEV_PMC_IO_DPD_REQ_0 :2bit). Because CSIC and CSID(APBDEV_PMC_IO_DPD2_REQ_0:10,11bit) is defunct.
    2. What is exactly means .id member of struct platform_device?
    3. Can I implementable CSI-B(x4, DSI) In r21.4 BSP?

    Thank you for reading for my poor English skill.
    Please reply my question.
    Best regard.

    were you able to verify if camera2 hardware is working using same v4l2 driver that was confirmed working for camera1?

    Yes I check the camera2 output line wave form to use oscilloscope.
    https://lh4.googleusercontent.com/-JDFu_umjhmQ/VoHdBlVODCI/AAAAAAAALZ0/boijRAr1MgU/w628-h471-no/2015-12-28.png