Jetson TK1 -- Enable ECC for DDR3L

How can I Enable ECC on the Tegra K1’s DDR3L mem?

This is not a feature of the Tx2:
https://devtalk.nvidia.com/default/topic/1000685/jetson-tx2/ecc-on-tx2/

but perhaps this is possible on the SOC?

Just learned that this is not so much something you enable, as something you can monitor.

Generally this is something built into the memory itself, but can be monitored via various utilities including:
https://www.linuxtechi.com/dmidecode-command-examples-linux/

and

https://linux.die.net/man/1/edac-util

Maybe this will help someone else.