Jetson TK1 IO cache coherency


I’m currently working on porting a driver to TK1, but I have run into an issue which I believe might be caused by a lack of IO cache coherence. Does anybody here know if TK1 is IO cache coherent, specifically the PCIe bus? Is this something I can enable or something that might show up in a future Tegra kit? I have looked in the TRM, but I didn’t find anything related.


This is probably (I can’t guarantee it) listed in the TRM for the ARM15 device, rather than for tegra124. Go here (you might need to create a login):

In the left column find “Cortex-A series processors”. Within this is “Cortex-A15 MPCore”. I’m not sure which revision best applies, probably just r4p0. This should describe every detail of the ARM15 built into tegra124, or at least get you started.

Thanks, that helps. As far as I understand from the ARM documentation, IO cache coherency is an optional part of the AXI bus protocol (ACE or ACP?), implemented on a per client/interface/device (?) basis. I assume that this depends on either the specific platform or specific interfaces for each platform.

From the block diagram in the TK1 TRM, I can see that something called “AFI” sits between the PCIe root ports and the AXI bus. I haven’t found any details about the AFI, but this is where I would expect to find details about cache coherency for PCIe on the TK1.

Just as reference, I see a diagram, figure 119, page 2261, section 32.0 of the Tegra K1 TRM. Is this the diagram you are looking at?

I cannot answer your question, but perhaps this will help. The Tegra K1 TRM, section, describes bit 11 of device control and device status registers. It seems that there are conditions under which the no snoop bit may be set, which implies hardware enforced cache coherency is no longer enforced. I have no idea under L4T as to whether this bit has been set or not, but it seems cache coherency may be hardware enforced if certain bits are not set.

Further related to this, bits 23 and 27 seem important. In the case of bit 27, apparently setting the bit non-coherency. Again, I do not know what these bits are set to under L4T, but it seems this could be a way of enabling/disabling what you need. Someone else would need to comment on how these are currently set and how changing those bits might break something else.