It seems that many of us are attempting a very similar procedure, setting up some form of SPI device on the TK1 that requires a SPI clock to be relatively low speed. There are many replies primarily in the grinch threads, but I figured I could start a new discussion on the subject, as the problem seems to span different kernel versions.
Following many tutorials on SPI, specifically @NeuroBots’s amazing tutorial: http://neurorobotictech.com/Community/Blog/tabid/184/ID/11/Using-the-Jetson-TK1-SPI--Part-1-Why-is-SPI-important.aspx, I was able to set up spidev for user-space access to the SPI-bus, but I am stuck attempting to reduce the SPI clock speed below 3.2MHz in order to interface my device.
Hooking the TK1 up to a logic analyzer shows that the SPI clock speed never drops below about 3.18MHz (as originally discovered by @neelfirst https://devtalk.nvidia.com/default/topic/823132/embedded-systems/-customkernel-the-grinch-21-3-4-for-jetson-tk1-developed/post/4575643/#4575643). Any attempt to set the speed lower than 3.2MHz (whether using the device tree or ioctl() commands) results in the TK1 reverting to the last speed that was faster than 3.2MHz.
Here is a snippet from my device tree corresponding to the spidev entry for reference:
spi@7000d400 {
compatible = “nvidia,tegra114-spi”;
reg = <0x7000d400 0x200>;
interrupts = <0x0 0x3b 0x4>;
nvidia,dma-request-selector = <0x7 0xf>;
nvidia,memory-clients = <0xe>;
#address-cells = <0x1>;
#size-cells = <0x0>;
status = “okay”;
spi-max-frequency = <25000000>;
spi0_0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <25000000>;
spi-cpha;
spi-cpol;
nvidia,enable-hw-based-cs;
};
};
I’m fairly certain that the spidev driver is allowing me to set the speed correctly. There are no errors using the ioctl() commands, and the device tree compiler has no complaints. I’ve enabled SPI debug mode in the kernel, and here is a snippet of two runs using two seperate SPI speeds from dmesg. Note the drop in frequency as was requested by me through spidev. In both cases, the speed remains at 3.5MHz (the initial speed above the lower bound), and both requested speeds are different than the spidev entry in the device tree, meaning that the commands are affecting the SPI bus speed, but only to a certain limit.
[ 7401.389176] spidev spi0.0: setup 16 bpw, cpol, cpha, 3500000Hz
[ 7401.389483] spidev spi0.0: setup mode 3, 16 bits/w, 3500000 Hz max → 0
[ 7401.389500] spidev spi0.0: spi mode 03
[ 7401.389521] spidev spi0.0: setup 16 bpw, cpol, cpha, 3500000Hz
[ 7401.389576] spidev spi0.0: setup mode 3, 16 bits/w, 3500000 Hz max → 0
[ 7401.389584] spidev spi0.0: 16 bits per word
[ 7401.389597] spidev spi0.0: setup 16 bpw, cpol, cpha, 3500000Hz
[ 7401.389645] spidev spi0.0: setup mode 3, 16 bits/w, 3500000 Hz max → 0
[ 7401.389652] spidev spi0.0: 3500000 Hz (max)
[ 7401.391912] spi-tegra114 spi-tegra114.0: The def 0x40c00000 and written 0x70c0182f
[ 7470.636012] spidev spi0.0: setup 16 bpw, cpol, cpha, 3500000Hz
[ 7470.636172] spidev spi0.0: setup mode 3, 16 bits/w, 3500000 Hz max → 0
[ 7470.636186] spidev spi0.0: spi mode 03
[ 7470.637516] spidev spi0.0: setup 16 bpw, cpol, cpha, 3500000Hz
[ 7470.637646] spidev spi0.0: setup mode 3, 16 bits/w, 3500000 Hz max → 0
[ 7470.637725] spidev spi0.0: 16 bits per word
[ 7470.637742] spidev spi0.0: setup 16 bpw, cpol, cpha, 1500000Hz
[ 7470.637804] spidev spi0.0: setup mode 3, 16 bits/w, 1500000 Hz max → 0
[ 7470.637812] spidev spi0.0: 1500000 Hz (max)
[ 7470.639482] spi-tegra114 spi-tegra114.0: The def 0x40c00000 and written 0x70c0182f
I’m pretty new to all this stuff, and I’m terrible at reading these things, but: On page 66 of the TRM, where the SPI clocks are referenced, it mentions a “Divide 8”. Based on the example, I assume this means 8-bit, but the division seems to cap at 4 bits:
50MHz/(2^4) = 3.125 MHz. (note 50MHz spec pulled from TRM pg 2443)
Am I overlooking something?
Any insight/new ideas would be a huge help.
Thanks,
Curtis