There are many clocks present in Camera VI unit like (sclk, vi, vi_sensor2, cile, isp, cilcd, pll_d, csi, emc)
Please refer to the Tegra K1 Technical Reference Manual link in Hardware Design and Development | NVIDIA Developer
The chapter 5.0 clock and reset controller have description for the clock source and register
basically,these are the clocks for internal block or module.
emc: external memory controller, a module that interfaces with external DDR/LPDDR device
vi: video input block
isp: image signal processor, a hardware engineer that is part of the camera processing pipeline
csi: MI-PI camera serial interface, a standard high-speed serial interface for connecting cameras to the K1
sclk: system clock
plld: clock for DSI and display controller
cile, cilcd: clock for csi
I am trying to connect 5MP camera to CSIE.
We are able to get 240p and 480p streaming by change cile clk. For 720p, 1080p and other resolution streaming to not working.
I have a idea about what each clock means, I even read the chapter 5.0 clock and reset controller in TRM(Technical Reference Manual). We don’t have any information about following things
1)**How these clock will effect the receiving MIPI data?
2)**How to use these clock according convenience?
What’s the camera module and type you using, is this a YUV camera and use V4L2 ?
How did you change cile clk ?
The camera module we are using is ov5640 , YUV format and using V4l2.
In drivers/media/platform/soc_camera/tegra_camera/vi2.c. In this file we have structure (struct tegra_camera_clk vi2_clks1). In this vi2_clks1 structure we have a name “cile clock” and by default it is 102MHz.
We changed the clock to 50MHzs it is working for 480p and 240p but not for resolutions like 720p, 1080p and 5MP.
Can you provide us more information about
1)**How these clock will effect the receiving MIPI data?
2)**How to use these clock according convenience?
3)*What is use of each clock?
1)**How these clock will effect the receiving MIPI data?
cile is the main clock for MIPI DPHY.
vi, csi are also required for VI/CSI block
2)**How to use these clock according convenience?
These clock settings are tested and verified in our Jetson TK1 with CIL_E sensor AR0261. It should be OK for OV5640.
3)*What is use of each clock?
vi - is the main clock for VI block.
csi - is the main clock for CSI block, it’s actually PLL_D_OUT0
vi_sensor2 - is the mclk for sensor, which sensor connecting to CIL_E needs that.
cile - is the clock for CIL_E which is the D-PHY clock. It has to be enabled for CIL_E sensor. 102MHz is the right frequency.
sclk, isp, emc are not required but it’s better we setup them as we do in the driver.
cilcd/cilab is for CIL_AB and CIL_CD and similar to cile
pll_d clock here is only for test pattern generator not for OV5640.
Would you please dump error status of the failure case like 720p and 1080p.
Please aware that CIL_E is just one data lane, it might not be enough to capture 5MP. we don’t think the clock setting here is the root cause.
If it’s possible it’s better to test it on CIL_AB with 2 lanes or 4 lanes.
Thanks for the reply Edli
We are aware that CIL_E is just one data lane. We also tested CIL_AB for 2lanes and 4lanes also. We are working on 1Lane for CIL_E. We are facing the issue with the clocks.
Reply for your Questions
1)Would you please dump error status of the failure case like 720p and 1080p.
Error Status
[ 108.475508] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00004190
[ 108.482864] TEGRA_VI_CSI_1_ERROR_STATUS 0x0000000d
[ 109.287969] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000013
Does it have same problem when tested on CIL_AB for 2 lanes or 4lanes ?
The MIPI could work up to 1.5Gbps, But the signal quality may be no good to work at higher frequency for wire rework.
It is working fine for CIL_AB. I don’t any problem.
Do you have idea about the above questions?
The 102MHz is a value we use for several sensors and we didn’t choose other value before.
The errors log means MIPI signal between Tegra and sensor has some problem, This might need to use scope to capture MIPI signal for further debugging.
is this sensor working on CIL_AB with 1 lane ?
We didn’t support YUV sensor in driver although hardware support, what’s kind of changes did you make ?
We don’t test the OV5640 sensor for 1Lane in CIL_AB
Just Enabled YUYV settings and at enable registers in code.
TEGRA_VI_CSI_1_CSI_IMAGE_DT
TEGRA_VI_CSI_1_CSI_IMAGE_SIZE_WC
TEGRA_VI_CSI_1_CSI_IMAGE_SIZE
Do you have any solution for my problem
1)How to proceed further to Debug the problem.
2) For ov5640 for 240p and 480p is working for cile=50Mhz and We dont know why it is not working for cile=102Mhz? Do u have any idea/answer/guess for this question? (This might helps us more)