1)**How these clock will effect the receiving MIPI data?
cile is the main clock for MIPI DPHY.
vi, csi are also required for VI/CSI block
2)**How to use these clock according convenience?
These clock settings are tested and verified in our Jetson TK1 with CIL_E sensor AR0261. It should be OK for OV5640.
3)*What is use of each clock?
vi - is the main clock for VI block.
csi - is the main clock for CSI block, it’s actually PLL_D_OUT0
vi_sensor2 - is the mclk for sensor, which sensor connecting to CIL_E needs that.
cile - is the clock for CIL_E which is the D-PHY clock. It has to be enabled for CIL_E sensor. 102MHz is the right frequency.
sclk, isp, emc are not required but it’s better we setup them as we do in the driver.
cilcd/cilab is for CIL_AB and CIL_CD and similar to cile
pll_d clock here is only for test pattern generator not for OV5640.
Would you please dump error status of the failure case like 720p and 1080p.
Please aware that CIL_E is just one data lane, it might not be enough to capture 5MP. we don’t think the clock setting here is the root cause.
If it’s possible it’s better to test it on CIL_AB with 2 lanes or 4 lanes.