Jetson TX1 MIPI CSI Calibration code base in L4T24.1 BSP

Hi All,

I am trying to locate exactly where MIPI CSI calibration and calibration settings are done in 24.1 code base.

The only function where I saw calibration settings configuration is:

tegra_dsi_mipi_calibration_XXx() in /drivers/video/tegra/dc/dsi.c

However it is felt that this piece of code is used only for DSI as these functions are not called when camera is initialized.

I expected MIPI CSI calibration to be in either of the below files, but could not locate any kind of MIPI CSI register access from these files as well.


Could you please guide me to the correct code portion in 24.1 BSP where MIPI CSI calibration is done?


Suppose the 24.1 didn’t implement the mipi calibration kernel driver yet.
Do you have any reason to move to 24.2.1 ?

Hi ShaneCCC,

Thank you for the response.

Suppose the 24.1 didn’t implement the mipi calibration kernel driver yet.
Not sure I understood this fully. Somewhere MIPI CSI calibration needs to be done, right?

Do you have any reason to move to 24.2.1 ?
I have a reference camera board working with 24.1, but not with 24.2. Hence sticking on to 24.1 to fix some timeout issue in new camera board.


If your sensor resolution and framerate are not pretty high the calibration are not really must necessary.

Hi, Shane

We need to support high resolution composite camera and need to do mipi csi calibration on 24.2.1. Do you have some documents on how to do it? I can see there are register settings for mipi-cal but in the TRM there are not much detailed explanations on how to use it.
More specifically, there are some brief description for dsi calibration in TRM, we need to do it for csi. Any pointer wrt them would be very helpful.

Adjustment based on PCB trace and layout
Since individual customer PCB boards have different trace length and characterizations, it may need to adjust the clock and data delays in individual lanes with the following registers.


If needed, we can move to 28.1 as well, although it would be nice to be able to do it on 24.2 since our current driver runs there

You can check the _tegra_mipi_calibration in mipi_cal.c and there’s a debug fs for debug.


Thanks for the info Shane. I added some log there because debugfs only output some counters. In my case the calibration is run, however the MIPI_CAL_CIL_CAL_STATUS_0 result is 1169b0/110000. From TRM section 30.2.3 it only save 15:12, 11:8 and 7:4 bits are debug bits but didn’t list what these values mean. We still have diffculties to get csi data, we get
[ +0.000083] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004000 —>>>HPA_UNC_HDR_ERR
[ +0.000983] csi2_cil_read:offset 0x00000010
[ +0.000498] vi vi: TEGRA_CSI_CIL_STATUS 0x00000013 ---->>> CILA_SOT_SB_ERR, CILA_SOT_MB_ERR and CILA_ESC_CMD_REC
[ +0.000053] csi2_cil_read:offset 0x00000014
[ +0.000065] vi vi: TEGRA_CSI_CILX_STATUS 0x00070070 ---->>> LANE0,LANE1 SOT SB and MB ERR
[ +0.000047] csi2_pp_read:offset 0x00000220
[ +0.000061] csi2_pp_read:offset 0x0000001c
[ +0.000296] vi vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004000
[ +0.000069] csi2_cil_read:offset 0x00000010
[ +0.000070] vi vi: TEGRA_CSI_CIL_STATUS 0x00000003
[ +0.000342] csi2_cil_read:offset 0x00000014
[ +0.000116] vi vi: TEGRA_CSI_CILX_STATUS 0x00030030

and debug counters have below values
[ +0.000065] vi vi: TEGRA_CSI_DEBUG_COUNTER_0 0x00000000
[ +0.000046] csi2_pp_read:offset 0x00000224
[ +0.002775] vi vi: TEGRA_CSI_DEBUG_COUNTER_1 0x00000001
[ +0.000084] csi2_pp_read:offset 0x00000228
[ +0.000127] vi vi: TEGRA_CSI_DEBUG_COUNTER_2 0x00000012
the counter 2 has different values each time. In TRM it mentions SOT SB and MB error indicates d-PHY level errors and need calibration.

I can see we might be able to adjust some calibration settings using some csi register based on the mipi_cal.c code. But I’m not sure what knobs to adjust. Do you know whether there are some more documents about how to calibrate mipi further?
BTW, I can see the HS mipi signals using a scope but I don’t have high accuracy mipi analyzer so I can only see the rough graph where frame data is in low voltage and a LP signal after each frame.


Some updates, I modified csi2_fops.c start streaming function and add some deley using CSI_CILA_PAD_CONFIG0_0, the maximum allowed is 7, which means 160ps. I also changed cil settle time there to 1 because our mipi signal transit from LP to HS directly. After these I can see CSI PHY level mostly working.

MIPI_CAL Sequence

1.Configure MIPI_CAL clock to the desired frequency: PLLP=408MHz, PLL_OUT3=68MHz
2. Release reset to MIPI_CAL via de-asserting SWR_MIPI_CAL_RST to 0
3. Configure DSI pads bias to the appropriate values according to MIPI_CAL PROD_Set
4. Configure Configure mipi calibration settings for DSI pads for set-up MIPI_CAL_DSI* _MIPI_CAL_CONFIG
5. Enable all the DSI / CSI lanes that require calibration driving LP_11 state
6. De-select the lanes (DSI / CSI) not in-use
7. MIPI calibration starts via - bit MIPI_CAL_STARTCAL in MIPI_CAL_MIPI_CAL_CTRL_0
8. Check MIPI_CAL status at MIPI_CAL_CIL_MIPI_CAL_STATUS_0, and MIPI_CAL_CIL_MIPI_CAL_STATUS_2_0, MIPI_AUTO_CAL_DONE has to be assert with values in a range of 1 to 14 in the fields MIPI_CAL_DRIV_DN_ADJ,MIPI_CAL_DRIV_UP_ADJ, and MIPI_CAL_TERMADJ, respectively.

Hi, Shane

thanks for the info. I did most of these step except #2, I see it mentioned in TRM as well but cannot find which bits and register is SWR_MIPI_CAL_RST defined.


SWR_MIPI_CAL_RST is bit 24 show as below.