Jetson TX2 architecutre is not same as Pascal architecture?

I was going through device query and visual profiler and found that it has 2 multiprocessor with 128 cuda cores/multiprocessor, while in Pascal architecture each sm has only 64 cuda cores. it seems it has similar number of cores as maxwell architecture.
Is it possible to have variable number of cores per multiprocessor for same architecture?

result from device query:

Device 0: “GP10B”
CUDA Driver Version / Runtime Version 8.5 / 8.0
CUDA Capability Major/Minor version number: 6.2
Total amount of global memory: 7854 MBytes (8235577344 bytes)
( 2) Multiprocessors, (128) CUDA Cores/MP: 256 CUDA Cores
GPU Max Clock rate: 1301 MHz (1.30 GHz)
Memory Clock rate: 13 Mhz
Memory Bus Width: 64-bit
L2 Cache Size: 524288 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(131072), 2D=(131072, 65536), 3D=(16384, 16384, 16384)
Maximum Layered 1D Texture Size, (num) layers 1D=(32768), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(32768, 32768), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: No
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0

Hi,

TX2 is in pascal family but for embedded system with 256 cores:
http://www.nvidia.com/object/embedded-systems-dev-kits-modules.html

I know this is embedded system. but as per pascal architecture each sm has 64 cores so according to you in pascal architecture sm can have 128 cores as well?

Hi,

Please check our document for details.
https://developer.nvidia.com/embedded/dlc/jetson-tx2-oem-product-design-guide

Each SM is partitioned into four separate processing blocks (referred to as SMPs), each SMP contains its own instruction buffer, scheduler and 32 CUDA cores. Inside each SMP, CUDA cores perform pixel/vertex/geometry shading and physics/compute calculations. Texture units perform texture filtering and load/store units fetch and save data to memory. Special Function Units (SFUs) handle transcendental and graphics interpolation instructions. Finally, the PolyMorph Engine handles vertex fetch, tessellation, viewport transform, attribute setup, and stream output.

Hi,

I came across the Pascal GP100 architecture and noticed that there are 8 load/store units per SMP.
I was wondering if this is also the case for the Jetson TX2 GPU’s SMPs.

Thank you for any help!

Best regards

Hi,

It looks like you already file a new topic for the question:
https://devtalk.nvidia.com/default/topic/1055146/jetson-tx2/jetson-tx2-pascal-gpus-load-store-units-/

Let us track the following status on the topic 1055146 directly.
Thanks.