Jetson TX2 Carrier Board PCIe Lane Numbering

Hi.

According to “Jetson TX1/TX2 Developer Kit Carrier Board Specification”, the J2 connector pin assignment is the following. It feels like to be reversed. Can I ask the reason of the order difference?

[PCIe#0 Lane0]
J2 B14 <-- PETp0 – PEX_TX4_P
J2 B15 <-- PETn0 – PEX_TX4_N
J2 A16 <-- PERp0 – PEX_RX4_P
J2 A17 <-- PERn0 – PEX_RX4_N

[PCIe#0 Lane1]
J2 B19 <-- PETp1 – PEX_TX3_P
J2 B20 <-- PETn1 – PEX_TX3_N
J2 A21 <-- PERp1 – PEX_RX3_P
J2 A22 <-- PERn1 – PEX_RX3_N

[PCIe#0 Lane2]
J2 B23 <-- PETp2 – PEX_TX2_P
J2 B24 <-- PETn2 – PEX_TX2_N
J2 A25 <-- PERp2 – PEX_RX2_P
J2 A26 <-- PERn2 – PEX_RX2_N

[PCIe#0 Lane3]
J2 B27 <-- PETp3 – PEX_TX1_P
J2 B28 <-- PETn3 – PEX_TX1_N
J2 A29 <-- PERp3 – PEX_RX1_P
J2 A30 <-- PERn3 – PEX_RX1_N

Thanks.

The PCIe specification allows for lane-reversal and polarity inversion to ease out routing. Refer to the official PCI-SIG document or books about PCIe, e.g. from Mindshare

danieel,

Thank you.