I designed a motherboard for TX1 and TX2 a few years ago, based on the OEM Product Design Guide for TX1 20161108. In this design guide the schematic around the Gigabit Ethernet interface was done using a classical transformer and only one capacitor to GND connecting the 4 primary mid-points of the transformer together. I made this motherboarc compliant for both TX1 and TX2 for all documented differences.
At the same time, the schematic of the DevKit for TX2 (revision B02 or B04) was using the same topology than the one described in the OEM Product Design Guide.
Recently, we were facing issues with autonegotiation for Gigabit Ethernet and we found that Nvidia changed the content of the OEM Product Design Guide by proposing to use 4 separated capacitors (one for each transformer primary mid-point) instead of a single one. We also saw that the latest revision of the DevKit (C02) was also using the 4-caps topology.
My question is: Why did Nvidia implemented this update? Was it related to actuel problems discovered with the Gigabit Ethernet Interface? Could you describe these problems?