We are currently working with a customer meaning to capture from a 64MP camera sensor (9248x6944), they are NOT planning to process the frame through the ISP (we know from a previous forum inquiry that the maximum line buffer width is 6144 for the ISP) nor encode the frame, they just want to dequeue the buffer from the sensor using the V4L2 framework.
Now, is there any limitation in the frame size for the VI block? I could not find any reference in the TRM.
Embedded Software Engineer
Suppose only have the MIPI D-PHY limitation. For TX2 devkit due to HW reason current only support 1G per lane. That tell if 4 lane you have 4G limitation. Then you can check the MAX support.
Thanks for the quick reply, based on your answer, the limitation would then apply to the maximum achievable frame rate but there should not be an issue to capture a frame of that size from the VI point of view. Is this correct?
Yes, also need to know the VI REG word count field is 16-bit, which means bytes per line should be < 2^16
Just to be clear, is it possible to capture with VI a 9248x6944 frame if we bypass the ISP?
Suppose can. But we didn’t verify it ever.
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