Jetson TX2 Memory

Hello everyone,

I have a question concerning the memory organization of Jetson TX2 with 8GB RAM: The memory controller of Parker SoC has 4 channels x 32 bit as an interface to LPDDR4 and x16 subpartitions are assumed. On the board we have 2 memory chips. If we consider the architecture of x16 LPDDR4, does that mean only 2 of the 4 channels and thus 64 bit bus width between memory controller and LPDDR4 are used for Jetson TX2 with 8 GB RAM?

Thank you in advance.

Best regards.

Hi, for Jetson Tx2, DDR is in module, customer only need to design carrier board and has no need to concern it.