# Jetson TX2 platform-level shared hardware timer **URL:** \ **Category:** Jetson TX2\ **Tags:** hw\ **Created:** [March 29, 2020, 12:51pm UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574 "2020-03-29T12:51:09Z")\ **Posts on this page:** 12\ **Page:** 1
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [March 29, 2020, 12:51pm UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/1 "2020-03-29T12:51:09Z")
Hi, I’m exploring the Jetson TX2 module. Specifically, I’m looking for a platform-level shared hardware timer that can be used by both CPUs (A57 and Denver2). Is there such thing available on the module? I haven’t found it (yet) on the documentation, keep looking for it. Thanks in advance. ---
**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\ **Post date:** [March 30, 2020, 11:24am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/4 "2020-03-30T11:24:01Z")
Hi takarto, Does watchdog timer meet your requirement? ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 1, 2020, 9:41pm UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/5 "2020-04-01T21:41:54Z")
Hi WayneWWW, I’ve been reading a bit more about the watchdog available on JetsonTx2 before answering. It seems all the documentation available reffer to what it is documented on Linux Kernel documentation, so I also checked Documentation/watchdog/watchdog-api.txt. I am looking for a hardware timer (it would be nice if it has autorefill capability) that is shared between both CPUs, i.e. once it expires it can trigger an event for every active core in the system, in this case I may need to look deeper on the GIC-400 which, as I understand, is available for both CPUs. So my main requirement is: -An external hardware timer (with auto refill ability is desirable). -That every core from both CPUs to be sensitive to the event when the timer expires. I am assuming that the wathdog, could meet such need (by using the pretimeout for example), however the main purpose of the watchdog is to monitor the CPU activity and call routines to recover the system. So, I would prefer not to limit it with my requirement and leave it for its original goal. That’s why I would preffer to use another external timer if available. Is there any? ---
**Author:** ![WayneWWW](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/waynewww/32/14043_2.png) [@WayneWWW](https://forums.developer.nvidia.com/u/WayneWWW)\ **Post date:** [April 6, 2020, 2:37am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/6 "2020-04-06T02:37:35Z")
Hi katarto, You could refer to the TX2 TRM (technical reference manual) from our download center and see if any other hardware timer is available. ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 6, 2020, 11:14am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/7 "2020-04-06T11:14:23Z")
Hi WayneWWW, Thank you for the reference. I will take a look on it and will reply here back with my findings. ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 8, 2020, 9:50pm UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/8 "2020-04-08T21:50:35Z")
Hi WayneWWW, In the TX2 trm (Parker\_TRM\_DP07821001p.pdf), it says that regarding the WDT if the expiration level is 3 or more, a normal interrupt (IRQ) routed to the LIC and from there routed to a set of processors. I found this interesting for my purpose. Now, I have the JetsonTX2 with L4T 4.9.140-tegra and Ubuntu 18.04. The built-in watchdog works as expected, rebooting the system when I am not kicking the WDT after the specified time (120s by default). In order to get a WDT with expiration level of 3 (to route the interruption to more than once processor) and without rebooting the system, I have to write the driver for it and build the kernel with it. Can you please confirm whether my understanding is correct? Also, according to TX2 trm (section 7.8.2), by using a TKE Module is possible to route the interruption generated by an NV Timer to shared interruptions. This can be also a good option. I have another question, if I want to use the TKE Module, is it possible to write the code, compile and run it from the L4T OS or do I have to do it from a host PC? ---
**Author:** ![shgarg](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/shgarg/32/9748_2.png) [@shgarg](https://forums.developer.nvidia.com/u/shgarg)\ **Post date:** [April 9, 2020, 11:22am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/10 "2020-04-09T11:22:46Z")
Hi takarto, You can use pps driver to fetch time of generated events. Add pps node in device tree: pps { gpios = \<&tegra\_main\_gpio TEGRA\_MAIN\_GPIO(I, 4) GPIO\_ACTIVE\_LOW\>; compatible = “pps-gpio”; assert-falling-edge; status = “okay”; }; You have to drive chosen GPIO pin externally based on your use-case. You can choose any GPIO present on 40-pin (J30) for this purpose. Here, I have used Pin 37 (GPIO I.04) on 40-pin connector of Jetson-Tx2 Flash with this dtb. When system boots, you will see sysfs node generated: ls /sys/class/pps/pps0/ Whenever event is generated on falling edge of signal (When GPIO pin value goes from high to low), timestamp will be captured using kernel timer and seen using: cat /sys/class/pps/pps0/assert If you want events to generate on rising edge of signal then remove assert-falling-edge; property from device node. Check if it serves your purpose. Thanks, Shubhi ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 10, 2020, 11:18am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/11 "2020-04-10T11:18:21Z")
Hi Shubhi, Thank you for your comment regarding the pps node. However, what I need is to know how to configure a **TKE Module** (which is mentioned on the TX2 technical reference manual) so I can generate an interrupt in the range of microseconds (or at least 1ms) and then to hook such interrupt to the LIC to have shared interrupts. (this is mentioned in section 7.8.2 Optional Interrupt Routing). Thanks in advance. ---
**Author:** ![shgarg](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/shgarg/32/9748_2.png) [@shgarg](https://forums.developer.nvidia.com/u/shgarg)\ **Post date:** [April 13, 2020, 7:15am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/12 "2020-04-13T07:15:47Z")
Hi takarto, Related to your previous query, you have to add watchdog property “nvidia,disable-por-reset;” in kernel device tree file under watchdog node : “watchdog@30c0000” for system not to reboot. And by default, expiration levels are \>=3. Also, it uses TKE shared interrupts. ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 13, 2020, 11:55am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/13 "2020-04-13T11:55:04Z")
Hi Shubhi, Thanks a lot! This will help me greatly. ---
**Author:** ![takarto](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@takarto](https://forums.developer.nvidia.com/u/takarto)\ **Post date:** [April 17, 2020, 11:14am UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/15 "2020-04-17T11:14:45Z")
Just adding few information from my findings to summarize: -Despite the good hint from Shgarg regarding how to avoid rebooting by the watchdog, it is not the solution to the original question. That’s why I unmarked it as solution. -WayneWWW pointed out to refer the TX2 TRM, which describes the TKE modules. Such modules contains: 16 timers and 4 watdog timers. Regarding the interrupts, from the TRM: “The interrupt routing block takes the set of interrupts present in the TKE and aggregates them in configurable fashion into nSI shared interrupts”. -Unfortunately, I did not find any way to access such timers from user space in Linux for Tegra. However there is a patch by Thierry Reding, which “Add native timer support on Tegra186”. Note: I have not tried this patch yet. However this is pointing out to answer to my original question. Thanks WayneWWW and Shubhi (Shgarg) for your support. ---
**Author:** ![nadeemm](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/nadeemm/32/367020_2.png) [@nadeemm](https://forums.developer.nvidia.com/u/nadeemm)\ **Post date:** [October 18, 2021, 6:18pm UTC](https://forums.developer.nvidia.com/t/jetson-tx2-platform-level-shared-hardware-timer/117574/16 "2021-10-18T18:18:29Z")