Jetson TX2i + Connect Tech Spacely Carrier PPS support

Hi folks,

I’ve been digging through the numberous articles on getting PPS support working on various carrier boards. I think i’m getting close, but need some help decyphering how the DTS file gets updated and how it know which GPIO to use.

L4T 32.5.0

Firstly, I’ve got tegra_defconfig setup with:


and my DTS file contains:

pps {
gpios = <&tegra_main_gpio 216 0>;
compatable = “pps-gpio”;
status = “okay”;

I am attempting to use GPIO 216 from the spacely GPIO expansion header.

It calls out P00 on P13 (pin 15), sysfs # 216. But the Pin is sourced via a TCA9539 at address 0x77.

I can’t find any reference in any of the Connect Tech DTS files that would show assigning one of the expansion GPIO to a special function like this.

My guess is my selection of the pin via the tegra_gpio_main 216 0 is wrong. Now looking through other DTS files, i can find:


i2c@3160000 {
status = “disabled”;
/delete-node/ lcd-bias-rails;

Does my pps section need to reside inside the gpio@77? does anyone have any experience in how to assign a gpio pin from a port expander to the pps gpio cell?

any help is appreciated.

Also, to add.

my current DTS compiles and flashes to target, but when it boots up i have no /dev/pps0 or /dev/pps1 devices.

and dmesg|grep pps just shows:

pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti

you should added pps{} device tree node into device tree, you may adding it anywhere inside dtb blob.
may I know which TX2 platform you’re used?
you could disassembler the dtb file into dts file for modification, $ dtc -I dtb -O dts -o temp.dts tegra-xxx.dtb
after that, please convert the DTS into a new DTB file, $ dtc -I dts -O dtb -o output.dtb temp.dts

the node, for example, $ ls /sys/class/pps/pps0/
it should be able to see via system filesystem after the device tree were added correctly.

Thanks Jerry

I’m using a TX2i with the Connect Tech Spacely carrier board.

My main question is: what is the format of the gpios line when I would like to use the spacely gpio pin 216 which is provided via a gpio expander (TCA9539).

I will check if the /sys/class/pps/pps0 is being created, i was under the impression it was /dev/pps0, so it could be there for all I know. will post once i confirm

/sys/class/pps/ is an empty folder, there is no pps0

hello mudrock,

please check below for all allocated GPIOs.
which pin you would like to use, the gpio-216 is registered as max77620-gpio.

$ dmesg | grep "registered GPIOs"
[    0.470230] gpiochip_setup_dev: registered GPIOs 320 to 511 on device: gpiochip0 (tegra-gpio)
[    0.474191] gpiochip_setup_dev: registered GPIOs 256 to 319 on device: gpiochip1 (tegra-gpio-aon)
[    0.516827] gpiochip_setup_dev: registered GPIOs 240 to 255 on device: gpiochip2 (tca9539)
[    0.518351] gpiochip_setup_dev: registered GPIOs 224 to 239 on device: gpiochip3 (tca9539)
[    0.563986] gpiochip_setup_dev: registered GPIOs 216 to 223 on device: gpiochip4 (max77620-gpio)
[    1.626053] gpiochip_setup_dev: registered GPIOs 208 to 215 on device: gpiochip5 (tca6408)

Hi folks,

wanted to close the loop.

After some feedback from CTI + tinkering, this is what works:

pps: pps_gpio {
gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(Y, 6) 0>;
compatible = “pps-gpio”;
status = “okay”;

along with the kernel config options i listed in the original message, on build, flash, boot up. You will now have a /dev/pps0 and /dev/pps1

The /dev/pps0 is the ktimer pps source, and /dev/pps1 will be triggered from the GPIO Port Y, Pin 6, which on the CTI Spacely carrier is P12, pin 17 (GPIO-IN). I beleive the ‘IN’ represents interrupt not input.

Once you have all that:

sudo apt install pps-tools

sudo ppstest /dev/pps0

should show timer triggers for each second the kernel timer is going.

sudo ppstest /dev/pps1

will show timer triggers for each pulse on the GPIO-IN pin. I can’t remember if it is rising or falling edge, but either way you get one timer trigger for each pulse.

Hope this helps other people

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