Jetson TX2i Debug UART0 and UART1 is not working

Dear Sir/Madam,

I am using Jetson TX2i module in my design, i am not able to access any UART0 and UART1.
I have not connected any Reset to Jetson in my design (ie., RESET_OUT and RESET_IN).
How to Debug weather my JETSON module is alive or not.

Dear Sir/Madam,

I had an issue with Jetson TX2i module.I have designed one Carrier Board for Jetson TX2i Module,now i had Connected Reset_OUT# to Jetson TX2i, Still i am not getting any prints on UART0 or UART2.
How to debug whether Jetson is working or not ? I have probed the Vin_PWR_BAD, Carrier_PWR_ON with respect to VDD_IN.
I had a Observation, my Vin_PWR_BAD is becoming active high late than Carrier_PWR_ON.
I am using one Inverter IC to make it Low, the falling edge of this signal (Inverter output has 7ms delay with respect to Vin_PWR_BAD).
Is this creates issue for Jetson to Boot please kindly clarify??

Hi, can you see USB device when connect Jetson to host pc? First you need to check the power up sequence as that listed in OEM DG, if no problem, it might be UART design issue which you should check the difference between your design and reference design.

Hi sir,

In my design, i am not using USB. Only UART i am using for communication between Jetson and Host.

I had a Observation, my Vin_PWR_BAD is becoming active high later than Carrier_PWR_ON.

The above point create any issue ?

Power up sequence is important, VIN_PWR_BAD# should be high earlier than CARRIER_PWR_ON.

Hi sir,

In my Carrier board timing from VDD_MOD to VIN_PWR_BAD# is 20 ms.
But timing from VDD_MOD to CARRIER_PWR_ON is 1ms.
According to OEM DG until VIN_PWR_BAD# is active Jetson Should not give Carrier_PWR_ON, because Tegra will not Power on until VIN_PWR_BAD# is active.
Can you please help me on this?

You need check the difference between your design and reference design to find out the root cause, also there is a checklist sheet in OEM DG which can help you to check items one by one.

Hi Sir,

According to OEM DG until VIN_PWR_BAD# is active Jetson Should not give Carrier_PWR_ON, because Tegra will not Power on until VIN_PWR_BAD# is active.

Is there any chance like Carrier_PWR_ON will be asserted before VIN_PWR_BAD# ?
I have compared our design with reference design, i have used reference design circuit to generate Power for Jetson, but Voltage is 12V in our design for Jetson. I am generating VIN_PWR_BAD# from TPS3808G01DBVR this IC after monitoring Jetson input Voltage.

During power on, VIN_PWR_BAD# is generated by a RC circuit which guarantee it rise high after VDD_IN reach threshold. TPS3808 is to monitor VDD_IN after system power on in case it drops below a threshold and then output to enable VIN_PWR_BAD#. You should check the RC circuit to see if any difference to reference design.