Jetson Xavier NX endpoint mode using E3317_A01 RX/TX Swap Board

Hi all,

we’re evaluating the Jetson Xavier NX for our products and we’ve planned to buy the Developer Kit for testing. We’re interested in configuring the NX in PCIe endpoint mode.
Is it possible to connect two NX Developer Kits together via PCIe, acting as master/slave, following NVIDIA Jetson AGX Xavier Series PCIe Endpoint Design Guidelines? Are there any special considerations for the Xavier NX that differs from Jetson AGX? Where can we find documentation about this configuration?
I know that the NX module supports it, but I wonder if this configuration is also possible using the DevKits using the same hardware/guidelines.


Yes. All the details mentioned in the AGX Endpoint design guidelines document should apply to NX as well except the fact that NX doesn’t have the typical PCIe CEM slot, but an M.2 Key-M slot. So, you may need to have the connecting cable/board for M.2 Key-M instead of CEM slot. With that aspect taken care of, everything else should work as is.

@vidyas Thank you for your quick response!

One more question: as per NVIDIA Jetson AGX Xavier Series PCIe Endpoint Design Guidelines the AGX need the TX/RX Swap. For the AGX there is a readily available solution (TX/RX Swap Module and PCIe Male-to-Male x8 Cable) is there anything similar for the Xavier NX? Should we build our own module?

There is not ready solution available for NX. You may have to build your own.

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@vidyas Sorry, one last question:

Is the TX/RX Swap Module available somewhere for purchase? In the documentation we see a lot of references to the E3317_A01 RX/TX Swap Board but can’t find it in the NVIDIA store…

I don’t think E3317 card as such is available for purchase from Nvidia store. The expectation is that customers should design their own looking at the schematics for E3317.
BTW, I stumbled upon the below link
and I think
|R22NS|PCI-E x4 ,connector to goldfinger, Tx to Rx signal swap|PCIe 3.0 x4 (32G/bps)|
|R22NF|PCI-E x4 ,connector to connector, Tx to Rx signal swap|PCIe 3.0 x4 (32G/bps)|
|R22NL|PCI-E x4 ,connector to connector, Tx to Rx signal swap|PCIe 3.0 x4 (32G/bps)|
|R22NR|PCI-E x4 ,connector to connector, Tx to Rx signal swap|PCIe 3.0 x4 (32G/bps)|
above configurations can be used.
Please note that I didn’t personally verify these cables. I just happen to find them when I was searching for the cables online.

@vidyas Thank you very much! That link was really usefull. I’ve notices that those cable don’t use any buffer (as per application note). Do we need them to connect the two kits?

Yes. We need those cables to connect both kits.


I’m sorry, I meant to say that the application note about the E3317 refers to a buffer (p/n SN74AUP1G07) that seems to be missing from the cable you linked. Is this buffer not needed or the cable has it and I failed to notice it?

Sorry. I forgot about those buffers. Yes. They are needed to avoid damage to the pads of PERST, WAKE and CLKREQ lines in case if there happen to be multiple active drivers. in AGX <-> AGX case, there are brief time periods when this (multiple drivers being active) happens. So, to avoid pad damage/reliability issues in the long run, you need to have a cable with this buffer or an equivalent circuit to accomplish the electrical isolation.

Hi, I’m a Mattia’s colleague and I’m starting to design the interconnection board between the two Jetson Xavier NX Dev Kits via M.2 Key M connector. We chose to use the R42SF, M.2 to PCIe 4x extender from ( ) and design a pcb for lane crossing and buffering of ctrl signals you mention above.
A doubt arises from the direction of reference clock PCIE0_CLK_P/N routed on M.2 key M connector of Xavier NX carrier board. In fact, reading the Jetson Xavier NX Datasheet at page 21, it’s not clear the direction of both pins PCIE0_CLK_n/p (pins# 160, 162), if Bidir or Output. In my opinion, only if it was bi-directional it could be configured as endpoint otherwise (output only) not.
On the other hand, on AGX carrier/SoM the ref clock sink/sources refer to separate pins connected to a mux on the carrier: reference clock 0 (balls E30, E31) is Input only (for a Xavier endpoint configured), while uses the separate PEX_CLK5 (balls F24, F25) clock out when the carrier is a Root Port.
Regardless of the possible inconsistency of the NX datasheet, can I simply connect directly the REFCLK+/- lane of the two adapters on my plug board?

Hi flavio.plos,

Welcome to Jetson & Embedded Systems forum, please open a new topic for your issue, we will support you through there.


did you find the answer to this and have you implemented a solution? looking to do similar

Hi Alan, I designed an interface but not tested yet.