We’re a little confused about how many SPIs are available/supported on the Xavier NX module. Table 10-6 of the Xavier NX Product Design Guide suggests that SPI is also available on GPIO03/04/05/06 and that this goes to SPI2 inside the SoC. However, Figure 10-2 only lists SPI1 and SPI3 as being available in the SoC, instead of all 3 SPI controller instances (SPI1/SPI2/SPI3) that the SoC has inside it. Is SPI2 functional/supported/validated for customer use?
In the v1.06 Xavier NX pinmux spreadsheet, it is not possible to select SPI2 functions for the SPI2 pins (spreadsheet drop-downs in cells AQ165 to AQ168); if SPI2 is indeed supported for customer use, could a fixed spreadsheet please be released?
It’s confusing because the SOC, the Module and the Device Tree all use different naming.
If you look in the Xavier SOC TRM, you’ll see it reference
Device
Address
spi1
0x03210000
spi2
0x0c260000
spi3
0x03230000
If you look at the Product Design Guide and the connector pin assignments you’ll see it reference module pin names of spi0* and spi1* and gpio3,4,5,6
Device
Pins
spi0
89,91,93,95,97
spi2
126,127,128,130
(as gpio3,4,5,6)
spi1
104,106,108,110,112
I think these names are 'generic" names because the pinout is shared across multiple module families. For instance, on the Nano SOC, they’re spi1 and spi2 mapped to module pin names spi0* and spi1*.
To make matters worse, the device tree has
Device
Address
spi0
0x03210000
spi1
0x0c260000
spi2
0x03230000
But there ARE 3 spi instances available on the SOC and they are mapped to the module names/pins as follows:
Are you looking at an older version of the Xavier SoC TRM? In version 1.4p, I can see:
In Section 3.1.2 (System Address Map):
SPI2: available @ 0x0c260000
SPI1: available @ 0x03210000
SPI3: available @ 0x03230000
This ties up with the device tree. In Section 10.5.1 (Serial Peripheral Interview, Overview) there is: “The Xavier SoC embeds three SPI controllers, each of which works independently of others”.
HA! you’re absolutely right. I didn’t see spi2 6 pages later. I updated the table in my previous post. In any case, it’s not brought out to the module pins so unless you’re using the Xavier SOC alone, it’s not available for use.
But the Xavier NX module Product Design Guide suggests it is brought out to the module pins, on GPIO03/GPIO04/GPIO05/GPIO06, module pins 126/127/128/130. These pins, supposedly, are SPI2_SCK/SPI2_MISO/SPI2_MOSI/SPI2_CS0* when in SFIO instead of GPIO. Table 10-6, SPI Signal Connections.
My apologies. I didn’t read far enough. :( I’m also hampered by the fact that I don’t have ready access to Excel to be able to use the spreadsheet. I can view it but that’s it. Also unfortunately nvidia doesn’t include the pinmux dtsi files any more. I guess they assume you’ll generate it from the spreadsheet.
In any case, by default the pins aren’t assigned to the spi2 controller so as you said in your first post,
either nvidia will have to update the spreadsheet or you’ll have to generate the default dtsi files and edit them to assign the pins to the spi2 controller.
Don’t worry, these things do happen :) … if it’s confusing enough for us on here, it will probably be confusing many other people, which is why I’m hoping nVidia will update the spreadsheet and provide clarity. Ideally, the Xavier NX module datasheet and Product Design Guide should also be updated to make the existence of SPI2 more clear…