JetsonTX2 PMU Denver2: BUS_ACCESS event

Hi all! My question is related to:
Board: JetsonTX2.
CPU: Denver2.
Feature: Performance Monitor Unit. (PMU, aslo known as Hardware Performance Counters).

I want to use Hardware Performance Counter to track the access per core to the shared memory.
In Cortex-A57 cores it is possible by using the event BUS_ACCESS present in the PMU of each ARMv8 core.

However, regarding Denver2 CPU (which both cores are almost an identical implementation of an ARMv8) such event (BUS_ACCESS) ist not supported.

From Parker Technical Reference Manual:
17.9.1 Common Performance Events

Denver 2 supports the common events described in the TRM except for events 0x19 (BUS_ACCESS) and 0x1D (BUS_CYCLES).

And the use of the uncore performance monitor event is not the solution for me because the events can not be identified per core.

Question:
1.- Is there any work-around to count accesses to shared memory per core in Denver2 cpu?
Besides using L2D_CACHE_REFILL and L2D_CACHE_WB together, which could do the work unless a write-through is performed.
2.- Is LL_CACHE_MISS (0x33) event available in Denver 2 cpu? The Tegra TRM include a table in section “17.9.1 Common Performance Events” up to event 0x1F.