JP 5.0.1 failed booting custom board

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
,
1

I haven’t had any luck booting my AGX custom board with JP5 (see my earlier posts in this forum).

Just saw 5.0.1 was released and tried it, still no luck, see below uart log

[0000.055] W> RATCHET: MB1 binary ratchet value 4 is larger than ratchet level 2 from HW fuses.
[0000.063] I> MB1 (prd-version: 2.2.0.0-t194-41334769-3540ffaa)
[0000.069] I> Boot-mode: Coldboot
[0000.072] I> Platform: Silicon
[0000.074] I> Chip revision : A02P
[0000.077] I> Bootrom patch version : 15 (correctly patched)
[0000.083] I> ATE fuse revision : 0x200
[0000.086] I> Ram repair fuse : 0x0
[0000.089] I> Ram Code : 0x5
[0000.092] I> rst_source: 0xb, rst_level: 0x1
[0000.097] I> Boot-device: SDMMC (instance: 3)
[0000.113] I> sdmmc DDR50 mode
[0000.116] I> Boot chain mechanism: A/B
[0000.120] I> Current Boot-Chain Slot: 0
[0000.124] W> No valid slot number is found in scratch register
[0000.129] W> Return default slot: _a
[0000.134] W> PROD_CONFIG: device prod data is empty in MB1 BCT.
[0000.139] I> Temperature = 37000
[0000.143] W> Skipping boost for clk: BPMP_CPU_NIC
[0000.147] W> Skipping boost for clk: BPMP_APB
[0000.151] W> Skipping boost for clk: AXI_CBB
[0000.155] W> Skipping boost for clk: AON_CPU_NIC
[0000.159] W> Skipping boost for clk: CAN1
[0000.163] W> Skipping boost for clk: CAN2
[0000.167] I> Boot-device: SDMMC (instance: 3)
[0000.176] I> Sdmmc: HS400 mode enabled
[0000.181] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000
[0000.187] W>  Thermal config not found in BCT
[0000.195] W>  MEMIO rail config not found in BCT
[0000.218] I> sdmmc bdev is already initialized
[0000.262] W>  Platform config not found in BCT
[0000.296] I> MB1 done

����main enter
SPE VERSION #: R01.00.18 Created: Jan 29 2021 @ 14:18:27
HW Function test
Start Scheduler.
in late init
��
[0000.305] I> Welcome to MB2(TBoot-BPMP) (version: default.t194-mobile-f46b9673)
[0000.306] I> DMA Heap @ [0x526fa000 - 0x52ffa000]
[0000.306] I> Default Heap @ [0xd486400 - 0xd48a400]
[0000.307] E> DEVICE_PROD: Invalid value data = 70020000, size = 0.
[0000.313] W> device prod register failed
[0000.317] I> Boot_device: SDMMC_BOOT instance: 3
[0000.321] I> sdmmc-3 params source = boot args
[0000.326] I> sdmmc-3 params source = boot args
[0000.329] I> sdmmc bdev is already initialized
[0000.338] I> Found 21 partitions in SDMMC_BOOT (instance 3)
[0000.344] I> Found 41 partitions in SDMMC_USER (instance 3)
[0000.345] W> No valid slot number is found in scratch register
[0000.350] W> Return default slot: _a
[0000.354] I> Active Boot chain : 0
[0000.381] I> Relocating BR-BCT
[0000.382]  > DEVICE_PROD: device prod is not initialized.
[0000.408] E> I2C: slave not found in slaves.
[0000.409] E> I2C: Could not write 0 bytes to slave: 0x00ae with repeat start true.
[0000.410] E> I2C_DEV: Failed to send register address 0x00000000.
[0000.411] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xae at 0x00000000 via instance 0.
[0000.412] E> eeprom: Failed to read I2C slave device
[0000.415] I> Failed to read CVB eeprom data @ AE
[0000.419] I> Retrying CVB eeprom read @ AC ...
[0000.424] E> I2C: slave not found in slaves.
[0000.428] E> I2C: Could not write 0 bytes to slave: 0x00ac with repeat start true.
[0000.436] E> I2C_DEV: Failed to send register address 0x00000000.
[0000.442] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xac at 0x00000000 via instance 0.
[0000.451] E> eeprom: Failed to read I2C slave device
[0000.456] I> Failed to read CVB eeprom data @ AC
[0000.472] I> Relocating OP-TEE dtb from: 0x6bfff0f0 to 0x70050000, size: 703
[0000.473] I> [0] START: 0x80000000, SIZE: 0x2f000000
[0000.474] I> [1] START: 0xaf200000, SIZE: 0x18a00000
[0000.477] I> dram_block larger than 80000000
[0000.481] I> [2] START: 0x100000000, SIZE: 0xf80000000
[0000.489] I> Setting NS memory ranges to OP-TEE dtb finished.
[0000.540] I> EKB detected (length: 0x410) @ VA:0x526ff400
[0000.541] I> Setting EKB blob info to OPTEE dtb finished.
��NOTICE:  BL31: v2.5(release):ef8af0b99
NOTICE:  BL31: Built : 20:57:59, May 16 2022
I/TC: 
��
��I/TC: Non-secure external DT found
��bpmp: init
bpmp: tag is 128431eec76692047e1ac1ebc0392266
sku_dt_init: not sku 0x00
clk_early initialized
mail_early initialized
fuse initialized
hwwdt initialized
t194_ec_get_ec_list: found 45 ecs
ec initialized
vmon_setup_monitors: found 3 monitors
vmon initialized
adc initialized
fmon_populate_monitors: found 73 monitors
fmon initialized
mc initialized
reset initialized
nvhs initialized
uphy_early initialized
emc_early initialized
��I/TC: OP-TEE versi��392 clocks registered
��on: 6f444acf (gcc version 9.3.0 (Buildro��clk initialized
��o��io_dpd initialized
��t��thermal initialized
thermal_mrq initialized
�� 2020.08))��i2c initialized
�� ��vrmon_dt_init: vrmon node not found
vrmon_chk_boot_state: found 0 rail monitors
vrmon initialized
��#2 Tue May 17��regulator initialized
�� 04:00:18 UTC 2022 aarch64
I/TC: Primary CPU initializing
��avfs_clk_platform initialized
soctherm initialized
aotag initialized
powergate initialized
dvs initialized
pm initialized
suspend initialized
pg_late initialized
pg_mrq_init initialized
strap initialized
nvl initialized
emc initialized
emc_mrq initialized
clk_dt initialized
tj_init initialized
uphy_dt initialized
uphy_mrq initialized
uphy initialized
ec_swd_poll_start: 281 reg polling start w period 47 ms
ec_late initialized
hwwdt_late initialized
reset_mrq initialized
ec_mrq initialized
fmon_mrq initialized
clk_mrq initialized
avfs_mrq initialized
mail_mrq initialized
i2c_mrq initialized
tag_mrq initialized
console_mrq initialized
mrq initialized
clk_sync_fmon_post initialized
��I/TC: ��clk_dt_late initialized
noc_late initialized
��P��pm_post initialized
dbells initialized
��rim��dmce initialized
��a��cvc initialized
��ry CPU switching��avfs_clk_mach_post initialized
�� to n��avfs_clk_platform_post initialized
��orm��cvc_late initialized
regulator_post initialized
��al w��rm initialized
console_late initialized
clk_dt_post initialized
��or��mc_reg initialized
��ld boot
��pg_post initialized
profile initialized
fuse_late initialized
extras_post initialized
bpmp: init complete
entering main console loop
] ��
Jetson UEFI firmware (version r34.1-975eef6 built on 2022-05-16T20:58:45-07:00)



3h


Jetson UEFI firmware (version r34.1-975eef6 built on 2022-05-16T20:58:45-07:00)
Press ESCAPE for boot options **  WARNING: Test Key is used.  **
......
ASSERT [L4TLauncher] /dvs/git/dirty/git-master_linux/out/nvidia/bootloader/uefi/Jetson_RELEASE/edk2/MdePkg/Library/BaseLib/String.c(37): String != ((void *) 0)

Resetting the system in 5 seconds.
3

You can try to compare the log before and after you apply the overlay. I believe you will notice the error is different.

Which means you are hitting a new issue.

You can build the UEFI binary by yourself, replace the binary to the debug version to enable more logs.

4
  1. Does JP 5.0.1 support customer board now? If not, maybe I should wait.
  2. When you said “before apply the overlay”, do you mean update Linux_for_Tegra/p2822-0000+p2888-0004.conf to empty the OVERLAY_DTB_FILE list? Since there is no change in rootfs or APP partition, is there an way to run flash.sh without re-writing the APP partition? Writing APP partition takes longest time and I am trying to avoid unless I make changes to the rootfs.
  3. When you said “build the UEFI binary” , are you referring to nvidia-l4t-jetson-uefi-source.tbz2 from here? Once compiled, replace bootloader/uefi_jetson.bin? What’s the flash.sh option to flash it to the board without reflashing everything?
5

Cleared OVERLAY_DTB_FILE list, re-flashed, and now get below boot error:

[0000.055] W> RATCHET: MB1 binary ratchet value 4 is larger than ratchet level 2
 from HW fuses.
[0000.063] I> MB1 (prd-version: 2.2.0.0-t194-41334769-3540ffaa)
[0000.068] I> Boot-mode: Coldboot
[0000.071] I> Platform: Silicon
[0000.074] I> Chip revision : A02P
[0000.077] I> Bootrom patch version : 15 (correctly patched)
[0000.082] I> ATE fuse revision : 0x200
[0000.086] I> Ram repair fuse : 0x0
[0000.089] I> Ram Code : 0x5
[0000.091] I> rst_source: 0xb, rst_level: 0x1
[0000.096] I> Boot-device: SDMMC (instance: 3)
[0000.113] I> sdmmc DDR50 mode
[0000.116] I> Boot chain mechanism: A/B
[0000.120] I> Current Boot-Chain Slot: 0
[0000.124] W> No valid slot number is found in scratch register
[0000.129] W> Return default slot: _a
[0000.134] W> PROD_CONFIG: device prod data is empty in MB1 BCT.
[0000.140] I> Temperature = 45500
[0000.143] W> Skipping boost for clk: BPMP_CPU_NIC
[0000.147] W> Skipping boost for clk: BPMP_APB
[0000.151] W> Skipping boost for clk: AXI_CBB
[0000.155] W> Skipping boost for clk: AON_CPU_NIC
[0000.160] W> Skipping boost for clk: CAN1
[0000.163] W> Skipping boost for clk: CAN2
[0000.168] I> Boot-device: SDMMC (instance: 3)
[0000.177] I> Sdmmc: HS400 mode enabled
[0000.181] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000
[0000.188] W>  Thermal config not found in BCT
[0000.196] W>  MEMIO rail config not found in BCT
[0000.218] I> sdmmc bdev is already initialized
[0000.263] W>  Platform config not found in BCT
[0000.297] I> MB1 done

����main enter
SPE VERSION #: R01.00.18 Created: Jan 29 2021 @ 14:18:27
HW Function test
Start Scheduler.
in late init
��
  [0000.305] I> Welcome to MB2(TBoot-BPMP) (version: default.t194-mobile-f46b967
3)
[0000.306] I> DMA Heap @ [0x526fa000 - 0x52ffa000]
[0000.307] I> Default Heap @ [0xd486400 - 0xd48a400]
[0000.308] E> DEVICE_PROD: Invalid value data = 70020000, size = 0.
[0000.313] W> device prod register failed
[0000.317] I> Boot_device: SDMMC_BOOT instance: 3
[0000.321] I> sdmmc-3 params source = boot args
[0000.327] I> sdmmc-3 params source = boot args
[0000.330] I> sdmmc bdev is already initialized
[0000.338] I> Found 21 partitions in SDMMC_BOOT (instance 3)
[0000.345] I> Found 41 partitions in SDMMC_USER (instance 3)
[0000.346] W> No valid slot number is found in scratch register
[0000.351] W> Return default slot: _a
[0000.354] I> Active Boot chain : 0
[0000.381] I> Relocating BR-BCT
[0000.383]  > DEVICE_PROD: device prod is not initialized.
[0000.408] E> I2C: slave not found in slaves.
[0000.409] E> I2C: Could not write 0 bytes to slave: 0x00ae with repeat start tr
ue.
[0000.410] E> I2C_DEV: Failed to send register address 0x00000000.
[0000.411] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xae at
 0x00000000 via instance 0.
[0000.411] E> eeprom: Failed to read I2C slave device
[0000.415] I> Failed to read CVB eeprom data @ AE
[0000.420] I> Retrying CVB eeprom read @ AC ...
[0000.425] E> I2C: slave not found in slaves.
[0000.429] E> I2C: Could not write 0 bytes to slave: 0x00ac with repeat start tr
ue.
[0000.436] E> I2C_DEV: Failed to send register address 0x00000000.
[0000.442] E> I2C_DEV: Could not read 256 registers of size 1 from slave 0xac at
 0x00000000 via instance 0.
[0000.451] E> eeprom: Failed to read I2C slave device
[0000.456] I> Failed to read CVB eeprom data @ AC
[0000.472] I> Relocating OP-TEE dtb from: 0x6bfff0f0 to 0x70050000, size: 703
[0000.473] I> [0] START: 0x80000000, SIZE: 0x2f000000
[0000.474] I> [1] START: 0xaf200000, SIZE: 0x18a00000
[0000.477] I> dram_block larger than 80000000
[0000.481] I> [2] START: 0x100000000, SIZE: 0xf80000000
[0000.489] I> Setting NS memory ranges to OP-TEE dtb finished.
[0000.541] I> EKB detected (length: 0x410) @ VA:0x526ff400
[0000.542] I> Setting EKB blob info to OPTEE dtb finished.
��NOTICE:  BL31: v2.5(release):ef8af0b99
NOTICE:  BL31: Built : 20:57:59, May 16 2022
I/TC:
��
  ��I/TC: Non-secure external DT found
��bpmp: init
bpmp: tag is 128431eec76692047e1ac1ebc0392266
sku_dt_init: not sku 0x00
clk_early initialized
mail_early initialized
fuse initialized
hwwdt initialized
t194_ec_get_ec_list: found 45 ecs
ec initialized
vmon_setup_monitors: found 3 monitors
vmon initialized
adc initialized
fmon_populate_monitors: found 73 monitors
fmon initialized
mc initialized
reset initialized
nvhs initialized
uphy_early initialized
emc_early initialized
��I/TC: OP-TEE versi��392 clocks registered
��on: 6f444acf (gcc version 9.3.0 (Buildro��clk initialized
��o��io_dpd initialized
��t��thermal initialized
thermal_mrq initialized
�� 2020.08))��i2c initialized
�� ��vrmon_dt_init: vrmon node not found
vrmon_chk_boot_state: found 0 rail monitors
vrmon initialized
��#2 Tue May 17��regulator initialized
�� 04:00:18 UTC 2022 aarch64
I/TC: Primary CPU initializing
��avfs_clk_platform initialized
soctherm initialized
aotag initialized
powergate initialized
dvs initialized
pm initialized
suspend initialized
pg_late initialized
pg_mrq_init initialized
strap initialized
nvl initialized
emc initialized
emc_mrq initialized
clk_dt initialized
tj_init initialized
uphy_dt initialized
uphy_mrq initialized
uphy initialized
ec_swd_poll_start: 281 reg polling start w period 47 ms
ec_late initialized
hwwdt_late initialized
reset_mrq initialized
ec_mrq initialized
fmon_mrq initialized
clk_mrq initialized
avfs_mrq initialized
mail_mrq initialized
i2c_mrq initialized
tag_mrq initialized
console_mrq initialized
mrq initialized
clk_sync_fmon_post initialized
��I/TC: ��clk_dt_late initialized
noc_late initialized
��P��pm_post initialized
dbells initialized
��rima��dmce initialized
cvc initialized
��ry CPU switching ��avfs_clk_mach_post initialized
��to n��avfs_clk_platform_post initialized
��orm��cvc_late initialized
regulator_post initialized
��al wo��rm initialized
console_late initialized
clk_dt_post initialized
��rl��mc_reg initialized
��d boot
��pg_post initialized
profile initialized
fuse_late initialized
extras_post initialized
bpmp: init complete
entering main console loop
] ��
    Jetson UEFI firmware (version r34.1-975eef6 built on 2022-05-16T20:58:45-07:
00)
ASSERT [PrePi] /dvs/git/dirty/git-master_linux/out/nvidia/bootloader/uefi/Jetson
_RELEASE/edk2/MdePkg/Library/BaseLib/String.c(638): Length < _gPcd_FixedAtBuild_
PcdMaximumAsciiStringLength

Resetting the system in 5 seconds.
6

Nope, that is not what I mean. If 5.0.1 is the first version you tried, then ignore what I said regarding the overlay.

Just focus on the uefi.

7

See attached uart log from booting with the debug uefi build.
flash-debug2.txt (85.9 KB)

8

Hi,

Did you change anything in UEFI or in the extlinux.conf?

Also, since this is custom board, did you also change the dtb? Could you share what you’ve modified in software?

9

For now I am trying to at least boot JP 5 unmodified, so there are no changes in UEFI, extlinux.conf or dtb.

10

What is the difference between your hardware and devkit?

11

I am closing this thread and will be working with Neel privately who knows our hardware details.

13

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