Jp 5.0.2 eqos compilation error on Jetson Orin

305248199 · September 5, 2022, 3:07am

In the kernel configuration file tegra_defconfig, configure the macro CONFIG_EQOS = y and report an error

Some compiled logs are as follows:
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:843:11: warning: ‘struct skb_frag_struct’ declared inside parameter list will not be visible outside of this definition or declaration
struct skb_frag_struct *frag,
^~~~~~~~~~~~~~~
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c: In function ‘eqos_map_page_buffs_64’:
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:847:31: error: dereferencing pointer to incomplete type ‘struct skb_frag_struct’
unsigned int page_idx = (frag->page_offset + offset) >> PAGE_SHIFT;
^~
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c: In function ‘tx_swcx_alloc’:
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:984:34: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
^
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:986:13: error: dereferencing pointer to incomplete type ‘struct skb_frag_struct’
len = frag->size;
^~
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:997:12: error: passing argument 3 of ‘eqos_map_page_buffs_64’ from incompatible pointer type [-Werror=incompatible-pointer-types]
frag, offset, size);
^~~~
/works/project/orin/kernel/nvidia/drivers/net/ethernet/nvidia/eqos/desc.c:841:12: note: expected ‘struct skb_frag_struct *’ but argument is of type ‘struct skb_frag_struct *’
static int eqos_map_page_buffs_64(struct eqos_prv_data *pdata,
^~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[6]: *** [/works/project/orin/kernel/kernel-5.10/scripts/Makefile.build:281: drivers/net/ethernet/nvidia/eqos/desc.o] Error 1
make[5]: *** [/works/project/orin/kernel/kernel-5.10/scripts/Makefile.build:498: drivers/net/ethernet/nvidia/eqos] Error 2
make[4]: *** [/works/project/orin/kernel/kernel-5.10/scripts/Makefile.build:498: drivers/net/ethernet/nvidia] Error 2
make[3]: *** [/works/project/orin/kernel/kernel-5.10/scripts/Makefile.build:498: drivers/net/ethernet] Error 2
make[2]: *** [/works/project/orin/kernel/kernel-5.10/scripts/Makefile.build:498: drivers/net] Error 2
make[1]: *** [/works/project/orin/kernel/kernel-5.10/Makefile:1854: drivers] Error 2
make[1]: *** Waiting for unfinished jobs…

Thank you

WayneWWW · September 5, 2022, 3:49am

Hi,

What is the purpose to enable EQOS? This driver is no longer supported on jetpack5.0.2.

305248199 · September 5, 2022, 3:51am

Gigabit Ethernet using rgmii interface

WayneWWW · September 5, 2022, 3:52am

The driver is also changed… we no longer support this driver.

If you want to run RGMII, try to read document… there is no need to build EQOS driver…

https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=rgmii#program-the-nvethernet-driver-dt-to-allow-it-to-work-with-the-third-party-phy-switch

305248199 · September 5, 2022, 3:57am

My DT file contents are:

    /* EQOS */
    ethernet@2310000 {
            status = "okay";
            nvidia,mac-addr-idx = <0>;
            nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
            phy-mode = "rgmii-id";
            phy-handle = <&phy>;

// /delete-node/ fixed-link;
nvidia,max-platform-mtu = <16383>;
mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <1>;
#size-cells = <0>;

                    phy: phy@0 {
                            reg = <0>;
                            compatible = "ethernet-phy-id001c.c916";
                            device_type = "ethernet-phy";
                            #if TEGRA_ETHERNETPHY_DT_VERSION >= DT_VERSION_2
                            /* use phy in poll mode */
                            #else
                            interrupt-parent = <&tegra_main_gpio>;
                            interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
                            #endif

// marvell,copper-mode;
/* Setup LED[2] as interrupt pin (active low) */
marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
};
};
};
};

305248199 · September 5, 2022, 5:46am

the pinmux changes:
pinmux@2430000 {
pinctrl-names = “default”, “drive”, “unused”;
pinctrl-0 = <&pinmux_default>;
pinctrl-1 = <&drive_default>;
pinctrl-2 = <&pinmux_unused_lowpower>;
pinmux_default: common {
eqos_txc_pe0 {
nvidia,pins = “eqos_txc_pe0”;
nvidia,function = “eqos”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};

                    eqos_td0_pe1 {
                            nvidia,pins = "eqos_td0_pe1";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };

                    eqos_td1_pe2 {
                            nvidia,pins = "eqos_td1_pe2";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };

                    eqos_td2_pe3 {
                            nvidia,pins = "eqos_td2_pe3";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };

                    eqos_td3_pe4 {
                            nvidia,pins = "eqos_td3_pe4";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };
                   eqos_tx_ctl_pe5 {
                            nvidia,pins = "eqos_tx_ctl_pe5";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };

                    eqos_rd0_pe6 {
                            nvidia,pins = "eqos_rd0_pe6";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };

                    eqos_rd1_pe7 {
                            nvidia,pins = "eqos_rd1_pe7";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };
                    eqos_rd2_pf0 {
                            nvidia,pins = "eqos_rd2_pf0";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };

                    eqos_rd3_pf1 {
                            nvidia,pins = "eqos_rd3_pf1";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
               };

                    eqos_rx_ctl_pf2 {
                            nvidia,pins = "eqos_rx_ctl_pf2";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };

                    eqos_rxc_pf3 {
                            nvidia,pins = "eqos_rxc_pf3";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };

                    eqos_sma_mdio_pf4 {
                            nvidia,pins = "eqos_sma_mdio_pf4";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    };

                    eqos_sma_mdc_pf5 {
                            nvidia,pins = "eqos_sma_mdc_pf5";
                            nvidia,function = "eqos";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                    };
                    soc_gpio17_pg4 {
                            nvidia,pins = "soc_gpio17_pg4";
                            nvidia,function = "rsvd0";
                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                    };
                   soc_gpio18_pg5 {
                            nvidia,pins = "soc_gpio18_pg5";
                            nvidia,function = "rsvd0";
                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                    };
            };
            pinmux_unused_lowpower: unused_lowpower {
            };
            drive_default: drive {
            };
    };

305248199 · September 5, 2022, 5:48am

The current situation is that the RGMII_TXC pin has a 125MHz clock. When other pins Ping other hosts, there is no signal

305248199 · September 5, 2022, 10:18am

boot log
luk-adu510_2022-09-05_18_16_15.log (329.7 KB)

WayneWWW · September 6, 2022, 2:48am

Please check adaptation guide first. This PHY and RGMII has been validated by many other users/customers already.

Make sure you do full flash instead of partial update in each time you change things. Device trees, or dtsi file.

And make sure the dtsi got flashed is indeed the file you modified…

305248199 · September 6, 2022, 3:13am

ADU506-RTL8211.pdf (141.7 KB)
rgmii 相关的原理图

quanz · September 6, 2022, 3:48am

The rgmii SCH is demaged.

305248199 · September 6, 2022, 3:53am

Is there a problem with this sch? Excuse me, what’s the problem?

quanz · September 6, 2022, 3:56am

305248199 · September 6, 2022, 4:03am

ADU506-RTL8211.pdf (141.7 KB)
retransmission

quanz · September 6, 2022, 9:03am

RGMII_TXC has 125MHz output, right?
“other pins other hosts, there’s no signal”, this is not clear, can you please list the pin names?
‘other host’ do you mean — RTL8211?

305248199 · September 6, 2022, 9:11am

yes，RGMII_TXC has 125MHz output .

rgmii rt8211DHCP cannot get IP,Manually set an orin rt8211 IP s,Ping other hosts;

The pins without signal are:
RGMII_TX_CTL
RGMII_TD0
RGMII_TD1
RGMII_TD2
RGMII_TD3

quanz · September 6, 2022, 9:30am

how about MDIO, does Orin get right info from MDIO?

305248199 · September 6, 2022, 9:35am

The correct ID number is obtained at startup: 0x001cc916 (rtl8211f); After that, it can correctly identify the inserted and unplugged network cables

305248199 · September 6, 2022, 9:46am

My DTS file’s
tegra234-p3711-ethernet.dtsi (1.5 KB)
tegra234-p3737-eqos-pinmux.dtsi (3.8 KB)
tegra234-soc-eqos.dtsi (7.5 KB)

WayneWWW · September 6, 2022, 9:50am

麻煩你就把dtb用dtc 轉成dts然後貼那個dts就好了不需要把每個dtsi都貼出來.

please just convert your final dtb back to dts by using dtc tool and just post that dtc tool. No need to paste every dtsi file here.

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Jp 5.0.2 eqos compilation error on Jetson Orin

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