IN TRM it is mentioned as
Pads that are associated with PMIC logic do not enter DPD mode during deep sleep: CLK_REQ,
CPU_PWR_REQ, PWR_INT_N, SHUTDOWN,SYS_RESET_N, CORE_PWR_REQ, CLK_32K_IN
Are this pads internal we are not able to find such pads in the Jetson module ?
What are the PMIC pads taken out in Jetson? Are they configurable in LP0 mode ?
CARRIER_PWR_ON is this pin configurable in LP0 mode ?
Is this pin connected to PMIC or JTX1 directly as the block diagram in OEM design guide shows it is connected to power section we assume that it is in pmic ?I assume that it is in PMIC am I correct
What are the GPIO Pads that supports LP0 mode how to use the GPIO in LP0 mode as High logic ?