L1/tex and texture memory in Maxwell Architecture

Accelerated Computing CUDA CUDA Programming and Performance
3

Thank you for your reply,

  1. I am using Jetson Nano,
  2. block(32,32), grid((M + block.x - 1) / block.x, (M + block.y - 1) / block.y); // M = 1000
  3. Yes the GPU clocks are locked
  4. For each kernel I launch 50 consecutive times
  5. inPtr type is uint8_t (unsigned char)

I posted another question related to the matter but using a simple program link which tries to explore the L1/L2 cache usage in Jetson Nano.

I tried compiling the code with const and restrict to achieve a cache read but the generated sass reports the same code. am I missing something here ?