L2 size per SM

According tot he deviceQuery for TitanV:

(80) Multiprocessors, ( 64) CUDA Cores/MP: 5120 CUDA Cores
L2 Cache Size: 4718592 bytes

I would like to know why L2 size is not a power of 2? Since it is shared among all SMs, each SM has 58982.4 bytes.
Or maybe that total number is the summation of somethings else and each SM has power of 2 slices.

The number of SMs (80) and the number of L2 slices are independent. The L2 slices that services a request is based upon the address not the requesting SM. The count in a chip is primarily determined by area. The memory system (L2 & devicememory) are shared resources used by the graphics engine (includes compute engine), copy engines, video engines, display controller, etc.

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