L4T R32.4.2's pinmuxing updates to p3310-1000-c03


I see this delta in the L4T 32.4.2 BSP from 32.3.1:

--- bsp.32-3-1/Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg   2019-12-10 07:02:49.000000000 +0000
+++ bsp.32-4-2/Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg   2020-04-09 02:26:24.000000000 +0100
@@ -1,8 +1,8 @@
-## Pinmux version 1.02
+## Pinmux version 1.04
 ## Input pinmux file name: tegra18x-jetson-tx2-config-template-pinmux.dtsi
 ## Input gpio file name: tegra18x-jetson-tx2-config-template-gpio-default.dtsi
-## Generation date: 2019-08-16 13:05
+## Generation date: 2020-03-31 11:08
 ## This is autogenerated file using the script pinmux-dts2cfg.py
@@ -251,7 +251,7 @@ pinmux.0x02439040 = 0x00004450; # eqos_r
 pinmux.0x02439030 = 0x00004450; # eqos_rd1_pe7: eqos, tristate-enable, input-enable
 pinmux.0x02439028 = 0x00004450; # eqos_rd2_pf0: eqos, tristate-enable, input-enable
 pinmux.0x02439020 = 0x00004450; # eqos_rd3_pf1: eqos, tristate-enable, input-enable, loopback-disable
-pinmux.0x0243906c = 0x00000450; # eqos_rx_ctl_pf2: eqos, tristate-enable, input-enable
+pinmux.0x0243906c = 0x00000458; # eqos_rx_ctl_pf2: eqos, pull-up, tristate-enable, input-enable
 pinmux.0x0243905c = 0x00000450; # eqos_rxc_pf3: eqos, tristate-enable, input-enable
 pinmux.0x02439038 = 0x00004448; # eqos_mdio_pf4: eqos, pull-up, tristate-disable, input-enable
 pinmux.0x02439048 = 0x00004400; # eqos_mdc_pf5: eqos, tristate-disable, input-disable
@@ -271,7 +271,7 @@ pinmux.0x0243601c = 0x00000448; # sdmmc4
 pinmux.0x02436018 = 0x00002448; # sdmmc4_dat5: sdmmc4, pull-up, tristate-disable, input-enable
 pinmux.0x02436014 = 0x00002448; # sdmmc4_dat6: sdmmc4, pull-up, tristate-disable, input-enable
 pinmux.0x02436010 = 0x00002448; # sdmmc4_dat7: sdmmc4, pull-up, tristate-disable, input-enable
-pinmux.0x0243600c = 0x00000450; # sdmmc4_dqs: sdmmc4, tristate-enable, input-enable
+pinmux.0x0243600c = 0x00000444; # sdmmc4_dqs: sdmmc4, pull-down, tristate-disable, input-enable
 pinmux.0x0c301080 = 0x00000401; # gpio_dis0_pu0: gp, tristate-disable, input-disable, lpdr-disable
 pinmux.0x0c301088 = 0x0000045a; # gpio_dis1_pu1: displaya, pull-up, tristate-enable, input-enable, lpdr-disable
 pinmux.0x0c301090 = 0x00000402; # gpio_dis2_pu2: dca, tristate-disable, input-disable, lpdr-disable

Q1) Do you have an explanation for the changes above? Are they important? Does it affect existing HW that is out in the field?
Q2) I don’t see version 1.04 of the TX2 Series pinmux spreadsheet released on the Download Center page. Can you please release it?
Q3) I see this change above for p3310-1000-c03.cfg (TX2) but not for p3489-1000-a00.cfg (TX2i) … is this an oversight, should TX2i have been updated as well with these changes?


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1.04 spreadsheet would released in next few days. Please follow up our dlc.

Thanks for the new spreadsheet on the DLC. I can see in the spreadsheet that both the TX2 and TX2i tabs were changed. This however does not seem to be reflected in the BSP source code, please see Q3 above.

This should not be fatal. Have you hit any error on your board?

No, no error, but I noticed the discrepancy and thought I should point it out…

I am still checking it with internal team. Waiting for their reply.

Hi, any updates on this? Thanks!

It looks like spreadsheet Revision History for 1.04 says ‘Change SDMMC4_DQS “Required Initial State” from “Z” to “PD”’ Shouldn’t it also have a comment that mentions the change to EQOS_RX_CTL also?

Was the change to EQOS_RX_CTL intentional in the pinmux cfg file?

EQOS_RX_CTL is an input pin on TX2 and is driven by the Ethernet PHY device on the module. The pull-up is to prevent Tegra input from floating. Ethernet PHY device, when not enabled, tristates its output to EQOS_RX_TL.

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Hi WayneWWW, any updates on the remaining question regarding the TX2i? Thanks!


There should be only Q3 waiting for reply, right?

Hi WayneWWW, yes, that’s right

Sorry for late reply.

That change is applicable to TX2i too.