LP for TX1 CSI interface

We are planning to interface FPGA to TX1 CSI interface, since FPGAs do not have native CSI interface, 4 pins for each lane will be needed to handle HS and LP according to Xilinx and Lattice.

Is LP really needed for TX1 kernel/dtb/driver/software?

We hope we can save a lot of FPGA pins without using LP.

Thanks in advance.

LP communication is needed in D-PHY protocol, i don’t think it can be ignored.