LP097QX1 eDP display - Timings not met

When attaching a LP097QX1 eDP display to the Nano, it refuses to drive it, as the Nano doesn’t think it can support the timings, I guess?

Its failing the “H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH <= 20” check in check_ref_to_sync() in nvidia/drivers/video/tegra/dc/mode.c.

The display works just fine when attached to various laptops and desktops with nvidia cards.

The datasheet for the display can be found here:
https://cdn-shop.adafruit.com/datasheets/LP097QX1-SPC1.pdf

According to it, H-Sync width is 5 cycles, H-Sync back-porch is 5 cycles and H_REF_TO_SYNC is set to 1 in the code. Added together, they are “11”, which certainly is less or equal to 20.

However, I don’t know enough about the DC to know where “20” comes from.

Any ideas on how to get some progress on this?

Have a check if below topic help on it.

https://devtalk.nvidia.com/default/topic/730349/jetson-tk1/display-port-expansion-on-jetson-tk1/2

Hi Shane!

Unfortunately, that topic doesn’t help me much, as it mostly covers the problems they had getting eDP/DP going on the TK1.

The Nano seems to have some kind of limitation on the minimum length of the total h-blank+sync period which I don’t understand.

Someone at nvidia with intimate knowledge about the display-controller should be able to answer if it’s possible for the nano to drive a panel with a total H-Sync+blank period of 11cycles.

Hi,

For tx1/nano, the constraint is H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 20 which is limited by the hardware capability.

Ok, that’s too bad, but thanks for the definitive answer.