When attaching a LP097QX1 eDP display to the Nano, it refuses to drive it, as the Nano doesn’t think it can support the timings, I guess?
Its failing the “H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH <= 20” check in check_ref_to_sync() in nvidia/drivers/video/tegra/dc/mode.c.
The display works just fine when attached to various laptops and desktops with nvidia cards.
The datasheet for the display can be found here:
According to it, H-Sync width is 5 cycles, H-Sync back-porch is 5 cycles and H_REF_TO_SYNC is set to 1 in the code. Added together, they are “11”, which certainly is less or equal to 20.
However, I don’t know enough about the DC to know where “20” comes from.
Any ideas on how to get some progress on this?