LPAE jetson support

Hello all!
I moved my question from build kernel thread where it was offtopic.

The question is: how can I enable support for more that 4GB address space per process?

It was promised by nvidia http://www.nvidia.com/object/tegra-k1-processor.html
and mentioned https://en.wikipedia.org/wiki/Tegra#Tegra_K1.

I enabled swap (16 gb), and I saw that my program took 3Gb mem and got “bad alloc”.
I downloaded last nvidia kernel sources (3.10.40), enabled LPAE, rebuilded all modules and flashed new kernel, but the only thing I’ve got is that network adapter became accessible. The program is still limited to 3GB.
It’s strange, that

cat /proc/cpuinfo

does not have lpae flag in features.

As far as I understand, LPAE support was added many years ago in kernel 2.6. I took vanilla kernel, and grepped for CONFIG_ARM_LPAE - yes, many entries.
That I did it on nvidia source tree … nothing.

So, that patches were threw away. Why?

Can anyone give me a piece of advice how to apply lpae patches from vanilla kernel to nvidia kernel source? Or it’s better to build vanilla kernel for jetson?

You have some custom board. If you absolutely sure that memory is wired and soldered properly search for a thread https://devtalk.nvidia.com/default/topic/724211/embedded-systems/jetson-tk1-ram-specification-clarification/2/. There is some info about enabling LPAE in this thread. Also there is info on lgeek github page https://github.com/lgeek/jetson_hw_hacking.

But lgeek forgot to add something on his github page so read the forum thread first

Hmm, board is not custom - 2Gb onboard memory, other mem is swap.
Yes, I have allready searched all devtalk and threads you have pointed. I have enabled LPAE without “Full 4Gb physical memory support”, because I have no 4Gb physical memory - 2Gb + swap. As far as I understand, swap != physical memory.
In any case, there are no #ifdefs CONFIG_LPAE in nvidia kernel source, though they can be found in vanilla kernel.

Correct me if I’m wrong, but isn’t it more or less impossible to use >4GB on a single process on a 32-bit processor?

I think that was the point, to make 4GB available via a combination of physical RAM plus swap. Without some kernel option changes and swap this full 4GB would not normally be available from a default kernel configuration. Additionally, although the CPU only deals in 32-bit spaces, the memory controller has some abilities to deal with 34 bits internally (see the TRM, section 16.5).

I see the option to enable CONFIG_LPAE in kernel config file (.config), you can enable it manually in arch/arm/tegra12_defconfig and do other changes as specified in https://github.com/lgeek/jetson_hw_hacking.
I also checked that LPAE support is added in the code already and you can search in git log (folder:- core) for “>2GB memory support”, there are other changes also like disabling dvfs and some in core-private & hwinc folder to support this.
It looks like you are not using the correct BCT config, since your configuration is not 4GB physical memory but 2GB+swap, so you might need to make changes in BCT accordingly. I will try to find out what changes you might need in this case.

sorry about previous observation, you don’t need any change in bct or dtb in this case, since the physical memory is still 2GB.
Please try to enable CONFIG_ARM_LPAE in kernel config file, and refer the changes from https://github.com/lgeek/jetson_hw_hacking.
(use the current 21.4 BSP)