LPDDR4 ReadLatency

Hi guys, please help.

I need to relax LPDDR4 read latency timing.

I understand RL(read latency) is defined in JEDEC Standards(JESD209-4A) Mode Register2(OP0-2).

I edited kernel DT source, tegra210-jetson-cv-emc-p2180-1000-a00.dtsi

emc-table@1600000 {
     ...
     nvidia,emc-mrw2 = <0x802002d>; //-> <0x802002e>
     // Read Latency@LP4-3200 32cycle -> 36cycle

     ...
}

I believe it’s correct.
But JTX1 doesn’t boot up.

I suspect TegraX1 other register timings need to be changed.
Are there any good tips?

Hi majin,

TX1 module is fixed and verified before ship out, and the characters of memory are tuning well too. JEP users only need to design their own carrier board, so why do you want to relax RL timing?

Hi Trumany,

That’s a shame!

I wanted memory overclocking.

Hi majin216,

As our previous comments, TX1 module is fixed and verified before ship out, and the characters of memory are tuning well too. To do the memory overclocking may cause system unstable hence that is not supported, Jetson user should not do with this type of change.

Thanks