LVDS 24BPP on Toradex Apalis TK1

I have successfully modified arch/arm/mach-tegra/panel-c-lvds-1366-4.c to drive my LVDS LCD connected to a Toradex Apalis TK1 SOM. I’m only getting activity on the LVDS lower 3 lines out of the SOM, not on the 4th, which may mean the TK1 is in 18BPP mode. I’ve tried setting dc->depth to 24 but it has no effect. How do I set the TK1 to 24BPP mode in that code? How can I see the TK1 LVDS/eDP mode?

The top of the file includes Copyright © 2013, NVIDIA CORPORATION licensed under GPL.

Thanks for any help.

Hi eric63,

Yes, it is a bug that missing to set current for lane4. Please try to add this patch to sor.

Subject: [PATCH] video: tegra: sor: set drive current for lane4

drive current for LANE4 was not set if configured as 24bpp lvds out.
fix it by programming proper drive current register if using 24bpp out.


diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index 7e81add..e3babe4 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -204,6 +204,7 @@
@@ -1901,6 +1902,9 @@
 	tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
 	tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
+	if (!conforming && (sor->dc->pdata->default_out->depth == 24))
+		tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum),
+		0x40);
 #if 0
 	tegra_sor_write_field(sor, NV_SOR_LVDS,
diff --git a/drivers/video/tegra/dc/sor_regs.h b/drivers/video/tegra/dc/sor_regs.h
index b1bb670..f906a1d 100644
--- a/drivers/video/tegra/dc/sor_regs.h
+++ b/drivers/video/tegra/dc/sor_regs.h
@@ -723,6 +723,7 @@
 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2			(43)
 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3			(51)
 #define NV_SOR_LANE_DRIVE_CURRENT(i)				(0x4e + (i))
+#define NV_SOR_LANE4_DRIVE_CURRENT(i)				(0x50 + (i))
 #define NV_SOR_PR(i)						(0x52 + (i))
 #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT				(24)
 #define NV_SOR_PR_LANE3_DP_LANE3_MASK				(0xff << 24)

Thanks. Lane4 is working now.