The device I’m talking to is made so that I need to keep CS asserted (low) between the transfers.
The “problem” is that I first have to send say 20 bytes and then depending on the response on MISO while sending these I have to send another 20 bytes which are depending on the result of the first - trouble is that I must keep CS asserted during this entire ordeal and only release it once I have all the bytes.
I saw that the SPI peripheral in the Tegra reference manual supports controlling the CS line by software using the bits:
CS_SW_HW and CS_SW_VAL
I’m just wondering if there’s support for it somehow?
(ii) When the transfer is the last one in the message, the chip may
* stay selected until the next transfer. On multi-device SPI busses
* with nothing blocking messages going to other devices, this is just
* a performance hint; starting a message to another device deselects
* this one. But in other cases, this can be used to ensure correctness.
* Some devices need protocol transactions to be built from a series of
* spi_message submissions, where the content of one message is determined
* by the results of previous messages and where the whole transaction
* ends when the chipselect goes inactive.
G16 can be made to work as a GPIO H.03 (#379). Try configuring it as a GPIO and manually setting it just as you have described. I would hope that the Tegra SPI driver will work, even though it is not in direct control of the SPI CS signal.