Mapping between UPHY lanes AND PEX clock and resets for Orin

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
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We found this mapping for PCIe C0 in the AGX Orin Design Guide

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Is this correct that C0 uses UPHY_TX0_P/N, and UPHY_RX0_P/N, and PEX_CLK1_N/P, and PEX_C1_CLKREQ_N, and PEX_C1_RST_N?

Is it correct that the signal names mentioned are NOT a typo?

Are you sure that PCIe port C0 does not go along with the signal names that contain C0 … for example PEX_CLK0_N/P?

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It is not a typo. Refer to Table 7-4. UPHY0 Mapping Options (USB & PCIe) and Table 7-15. PCIe Control Pin Descriptions in AGX Orin Design Guide.