Max trace length for CAN bus interface

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I’m looking at table 79 of the TX2 OEM Product Design Guide (http://developer.nvidia.com/embedded/dlc/jetson-tx2-oem-product-design-guide), and I don’t fully understand the Max Trace Length parameter. The specified requirement (for RX and TX) is 223mm. However, the Jetson carrier board brings those signals out to the GPIO Expansion Header, and the distance between the Tegra socket and the GPIO expansion header is significantly longer than that, even in a straight line.

Am I misinterpreting the table or does the Jetson carrier board use some design techniques to get around the trace length limit?

Also, the Max Trace Length row of Table 79 also says “See Note 2”, but there doesn’t appear to be a “Notes” section within chapter 12.5 Is it missing?

2

Since neither the CANx_TX or CANx_RX are differential signals neither of the following items in table 79 make sense

Max Trace Length (for RX & TX only)
Max Trace Length/Delay Skew from RX to TX

3

The guidelines would be from the Jetson TX1 CAN pins to the CAN bus driver, the TX/RX line length on carrier board are about 133 mm, not exceed the requirement (233 mm).

4

Thank you for your clarification Trumany. I just had a brainfart while thinking about the 233mm and mentally converted it incorrectly.