Max9295 + max9296 + imx390 serdes camera v4l2 status is no power

Thx to reply ShaneCCC

Result is still not work … because mipi didnt get any data …
so i asked FPGA and they said that ‘Check DT and csi or mipi setting before adjust registers’.

my Question is i want to know about CSI’s pin point
so my CSI pin points are here and Am I missing some points?


hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-imx390-a00.dtsi

	nvcsi@150c0000 {
			num-channels = <2>;
			#address-cells = <1>;
			#size-cells = <0>;
			channel@0 {
				reg = <0>;
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						imx390_csi_in0: endpoint@0 {
							port-index = <0>; // vc
							bus-width = <2>;
							remote-endpoint = <&imx390_imx390_out0>;
						};
					};
					port@1 {
						reg = <1>;
						imx390_csi_out0: endpoint@1 {
							remote-endpoint = <&imx390_vi_in0>;
						};
					};
				};
			};
			channel@1 {
				reg = <1>;
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						imx390_csi_in1: endpoint@2 {
							port-index = <0>;  // vc
							bus-width = <2>;
							remote-endpoint = <&imx390_imx390_out1>;
						};
					};
					port@1 {
						reg = <1>;
						imx390_csi_out1: endpoint@3 {
							remote-endpoint = <&imx390_vi_in1>;
						};
					};
				};
			};
		};
	};



//.. 

i2c@3180000
imx390_b@1c // check reply!
dynamic_pixel_bit_depth = “24”;
csi_pixel_bit_depth = “24”;
mode_type = “rgb”;
pixel_phase = “rgb888”;
//…

tegra-camera-platform {
	compatible = "nvidia, tegra-camera-platform";
            // ...
	num_csi_lanes = <2>;
	max_lane_speed = <4000000>;
	min_bits_per_pixel = <10>;
	vi_peak_byte_per_pixel = <2>;
	vi_bw_margin_pct = <25>;
	isp_peak_byte_per_pixel = <5>;
	isp_bw_margin_pct = <25>;

	i2c@3180000 {
			imx390_a@1b {
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						imx390_imx390_out0: endpoint {
							status = "okay";
							vc-id = <0>;
							port-index = <0>;
							bus-width = <2>;
							remote-endpoint = <&imx390_csi_in0>;
							};
						};
					};

// ...
				gmsl-link {
					src-csi-port = "b";
					dst-csi-port = "b"; // HW dependency
					serdes-csi-link = "a";
					csi-mode = "1x4";
					st-vc = <0>;
					vc-id = <0>;
					num-lanes = <2>;
					//streams = "ued-u1", "raw12";
					streams = "ued-u1", "rgb888"; // TEST
					};

imx390_b@1c {


				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						imx390_imx390_out1: endpoint {
							vc-id = <1>;
							port-index = <0>;
							bus-width = <2>;
							remote-endpoint = <&imx390_csi_in1>;
							};
						};
					};
				gmsl-link {
					src-csi-port = "b";
					dst-csi-port = "b"; ; // HW dependency
					serdes-csi-link = "b";
					csi-mode = "1x4";
					st-vc = <0>;
					vc-id = <1>;
					num-lanes = <2>;
					streams = "ued-u1", "rgb888"; // // TEST
					};

Looks like lost the "vc-id = <>;"in the imx390_imx390_out0/imx390_imx390_out1, But shouldn’t matter with NVCSI/VI didn’t receive validate data. Did you probe the MIPI signal to confirm it?

Thx to reply

Code was mixed up when i edit comment anyway…

MIPI signal is not reached so i struggled that.
I think that FPGA and SERDES register setting is not matched
but FPGA sides said my DT and CSI setting is wrong .

I never using Tegra before and not sure is it right. that is reason why i ask that

finally i fixed DT and devices and success to capture from v4l2-ctl
captureing data is works good but gstreamer is not working


VIDIOC_QUERYCAP: ok
VIDIOC_S_EXT_CTRLS: ok
VIDIOC_G_FMT: ok
VIDIOC_S_FMT: ok
Format Video Capture:
        Width/Height      : 1920/720
        Pixel Format      : 'AR24'
        Field             : None
        Bytes per Line    : 7680
        Size Image        : 5529600
        Colorspace        : sRGB
        Transfer Function : Default (maps to sRGB)
        YCbCr/HSV Encoding: Default (maps to ITU-R 601)
        Quantization      : Default (maps to Full Range)
        Flags             :
VIDIOC_REQBUFS: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_QUERYBUF: ok
VIDIOC_QBUF: ok
VIDIOC_STREAMON: ok
VIDIOC_STREAMOFF: ok
data is looks fine 

(CMD) gst-launch-1.0 v4l2src device=“/dev/video0” ! “video/x-raw, format=BGRA, width=1920, height=720, framerate=30/1” ! videoconvert ! xvimagesink

Setting pipeline to PAUSED …
Pipeline is live and does not need PREROLL …
Pipeline is PREROLLED …
Setting pipeline to PLAYING …
New clock: GstSystemClock
ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Internal data stream error.
Additional debug info:
…/libs/gst/base/gstbasesrc.c(3127): gst_base_src_loop (): /GstPipeline:pipeline0/GstV4l2Src:v4l2src0:
streaming stopped, reason not-negotiated (-4)
Execution ended after 0:00:00.001330112
Setting pipeline to NULL …
Freeing pipeline …

Can I get next steps?

Could you try below command.

gst-launch-1.0 v4l2src device=/dev/video0 ! 'video/x-raw, format=BGRA, width=1920, height=720, framerate=30/1' ! xvimagesink

gst-launch-1.0 v4l2src device=/dev/video0 ! 'video/x-raw, format=BGRA, width=1920, height=720, framerate=30/1' ! nvvidconv ! xvimagesink

1st result is…

Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Pipeline is PREROLLED ...
Setting pipeline to PLAYING ...
ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Internal data stream error.
Additional debug info:
../libs/gst/base/gstbasesrc.c(3127): gst_base_src_loop (): /GstPipeline:pipeline0/GstV4l2Src:v4l2src0:
streaming stopped, reason not-negotiated (-4)
ERROR: pipeline doesn't want to preroll.
Execution ended after 0:00:00.000163552
Setting pipeline to NULL ...
Freeing pipeline ...

2nd result


0:00:00.085972192  8624   0x5580ae32f0 ERROR           GST_PIPELINE gst/parse/grammar.y:760:gst_parse_perform_link: could not link v4l2src0 to nvvconv0, nvvconv0 can't handle caps video/x-raw, format=(string)BGRA, width=(int)1920, height=(int)720, framerate=(fraction)30/1
WARNING: erroneous pipeline: could not link v4l2src0 to nvvconv0, nvvconv0 can't handle caps video/x-raw, format=(string)BGRA, width=(int)1920, height=(int)720, framerate=(fraction)30/1

not works all

May need to trace the v4l2src to get more information.

Have modify or remove the format in command line for try and error.

format=BGRA

YEP problem was unstable signals


GST_DEBUG=3 gst-launch-1.0 v4l2src device=/dev/video0 ! "video/x-raw, format=BGRA, width=1920, height=720, framerate=30/1" ! queue ! videoconvert ! clockoverlay !  nveglglessink -v

is works

HI ShaneCCC

I still have problem with RGB24 settings.
I cheched streaming sender’s signals.

sender’s image is

but TX2 rgb24 is this.

#gst-launch-1.0 v4l2src device=/dev/video0 ! “video/x-raw, format=BGRA, width=1920, height=720” ! videoconvert ! xvimagesink -v

Other v4l2src format likes ARGB or BGRx is not working and i added RGB24 too

RGB888 should be report to AR24 by v4l2-ctl --list-formats-ext