Maximum frequency of extperiph1


I would like to know if it is possible to increase extperiph1 frequency to 75MHz.

According to /sys/kernel/debug/bpmp/debug/clk/extperiph1/max_rate, maximum frequency of extperiph1 is 37,090909 MHz. Why is this the maximum value, and can it be increased? Parent clock of exterpiph1, PLLP, generates 408 MHz.

CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0 register described in the Technical Reference Manual contains a divisor EXTPERIPH1_CLK_DIVISOR. I would expect that the maximum frequency of extperiph1 is reached when this divisor is set to 0. However, minimum value of this divisor seems to be 0x14. This is the value that divisor contains when extperiph1 is set to its maximum frequency of 37,090909 MHz. Where does this limitation come from and can it be circumvented in software?

For context, we are trying to use extperiph1 as a master clock for an image sensor in the same way that it is used for OV5693 sensor that is shipped with TX2. Only difference is that we would like the clock to be at 75MHz, and not at 24MHz as in OV5693. Is this possible to achive? Or is it necessary to provide an external clock for this frequency?

Thank you!

hello dominik.zebec,

please check below chapter in TX2 TRM for more details.
[CLOCK CONTROLLER]-> [PLLs in the System and Primary Usage]

also, there’s clock multiplier for your configuration.
please check your sensor spec. to set correct MIPI clock.

What is the name of this multiplier in TRM? How can I set this multiplier to a desired value? Can I set it in driver, in device tree or in /sys/kernel/debug/?

I have already read the “PLLs in the System and Primary Usage” chapter.

Sensor datasheet requires input frequency of 75 MHz (74.25 MHz to be more precise). This is the frequency I am trying to achieve at extperiph1.

hello dominik.zebec,

please check sensor device tree.
paste code snippet as below for reference.

mode0 { // OV5693_MODE_2592X1944
    mclk_khz = "24000";
    mclk_multiplier = "6.67";

Modifying this value in device tree doesn’t seem to change frequency of extperiph1 as reported in /sys/kernel/debug/bpmp/debug/clk/experiph1/rate.

I tested this by modifying the device tree for OV5693.

I modified hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-e3326-a00.dtsi in the following way:

mode1 { //OV5693_MODE_2592X1458
    mclk_khz = "20000";
    mclk_multiplier = "8.00";

I also removed mode2 in order to confirm that TX2 in really using the modified device tree.

I compiled the kernel, then flashed the resulting device tree using dd:

sudo dd if=tegra186-quill-p3310-1000-c03-00-base.dtb of=/dev/mmcblk0p25

I tested the results using argus_camera example.

When the mode was set to 0, /sys/kernel/debug/bpmp/debug/clk/experiph1/rate was at 24 MHz.
When the mode was set to 1, /sys/kernel/debug/bpmp/debug/clk/experiph1/rate was still at 24 MHz, despite the device tree being modified to set it at 20 MHz.
Mode 2 did not exist, confirming that the device tree was really modified.

Is there something I am missing here?

hello dominik.zebec,

because extperiph1 is default clock source.
you should look into kernel driver instead of clock tree.

here are device tree probing functions for your reference.
please check mclk_khz and pix_clk_hz for more details.


static int sensor_common_parse_signal_props()

If I understood this correctly, frequency of extperiph1 (as reported in /sys/kernel/debug/bpmp/debug/clk/experiph1/rate) and input frequency of sensor (as defined in mclk_khz) are two separate values. Is this correct? What is their exact relationship?

Back to my original question, does this mean that I simply have to set mclk_khz to 74250, adjust the mclk_multiplier and the input clock of the sensor will be set to 74.25MHz? Will I be able to measure this frequency on CAM0_MCLK pin with an oscilloscope?

hello dominik.zebec,

the mclk tegra given is sensor input clock,
please check your sensor specification, there should be a diagram shown the PLL configuration.


I also need to modify “extperiph1” in order to decrease the frequency.

The file ./soc/t18x/kernel-include/dt-bindings/clock/tegra186-clock.h mentions that “extperiph1” is controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1.

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
#define TEGRA186_CLK_EXTPERIPH1 89

I think the CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0 should be configured by some specific driver for tegra platform, I have done a general search in the kernel in order to locate who performs this task but I have not been lucky.

Has someone been able to change extperiph1 frequency?


hello ManuelLeiva,

we had fixed extperiph1 clock rate for TX2,
you should modify the clock frequency by change the mclk_multiplier.