Mechanical tolerances and thermal performance Jetson Nano


I’m currently working on thermally interfacing a Jetson nano-board to a chassis.
To use an as thin as possible thermal pad I’m trying to calculate the overall tolerance of the system, and I cannot find the tolerances on the Tegra X1 chip.
I would also like the thermal performance of the chip (i.e Psi JT)

A complete datasheet for the Tegra X1-chip might be what I’m looking for but cannot find.

Thanks for any help.

Hi, there is module with cover outline in Module Datasheet for your reference, We do not provide chip thermal performance, as you can see in Thermal DG, Jetson Nano enables a wide variety of applications that may exercise different components on the module. The variation between applications will cause variation in heat loads on the different components on the Jetson Nano and hotspots in different logical partitions of the Tegra X1. While the system thermal solution will help to spread the heat and make the thermal performance as consistent as possible, different applications will have different levels of thermal performance. The more evenly the module power is distributed across the Jetson Nano the higher the thermal performance will be.


I’ve found the drawing in the Datasheet, but there is no tolerances stated, i.e. how much the thickness differ between the modules. E.g the tolerances on board height in the SO-DIMM-socket used are 7.3mm +0.25/-0.00 mm.

For our thermal solution I’m assuming we’re drawing full power, 10W.
The Thermal DG only has a reference to the maximum Junction temperature of the silicon, without the heat transfer parameters I cannot accurately calculate how good the rest of my thermal solution needs to be.
To accurately calculate the junction temperature I need to consider the thermal resistance of the chip packaging, this figure is not mentioned in the Thermal DG.
Or can I assume that the heat transfer between the junction and case top is so good that we’re talking below 1 degree C and can be disregarded?


We are checking if such tolerance data can be shared.

As for the thermal design, the guide gives the way to design a thermal solution which should be attached on chip and on other points directly, so it uses Tcpu=93C, TMP=10W in general, you can refer to that to calculate θja in theory with Tamb you want. You can treat Tcpu as the surface temperature of chip.


The tolerance of the height of SoC is 2.28mm +/- 0.15mm.


Thank you for your help Trumany!

Best Regards