We are looking for ways to spot soldering issues on memory address and data lines on boards equipped with a Tegra K1 processor. Looking into tests others are doing to detect shorts in address lines, we came across what is implemented and described in the u-boot POST memory tests:
Unfortunately this kind of test (shifting a single high resp. low bit through the memory address range with all other bits being fixed) does not seem to detect any errors for us. For testing we manually cut the A7 address line on a board, so this one is open - simulating a bad soldering.
Our hardware setup uses 4 blocks of 4Gb memory, providing a total of 2GB memory to the Tegra. What is unclear to us is how the mapping of memory addresses in the CPU range (0x80000000 - 0xffffffff) to the physical address lines (bank selection + row/column addressing) is actually looking like. Reading the TRM I understand that CPU memory access is not routed through the SMMU but through a dedicated internal MMU, is this correct? If so, is there a way to disable this MMU and if not is there any description on how it would map the addressing?
Furthermore I am wondering if there might be any caches besides L1 Data-Cache and L2 that could be affecting such kind of a memory test? We are running this test out of early u-boot init, before u-boot relocates it’s stack to DRAM, so that we can operate the full DRAM during tests. L1 D-Cache is disabled and L2 should not be enabled at that stage at all.
Besides understanding how the memory address is actually working on the TK1 I would be interested in any thoughts about how sane this kind of memory test is on the TK1? Are there possibly better tests, which are comparably simple? Doing an exhaustive r/w test is to be avoided in this case, but a quick line-tester is the primary goal.
Thanks for your thoughts!