Memory address mapping issues in GPU architecture

It is known that each physical address is composed with rank, row, column, channel and byte offset.
I learnt from Gpgpu-sim[1] that the address mapping scheme in GTX480(Fermi) architecture is

00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
Where R®=row, B(b)=bank, C©=column, S(s)=Burst.

  1. I am curious that how did they find out this address mapping scheme?
  2. And whether this address mapping scheme can be applied to other GPU architecture like Tesla K80(Kepler) and GTX980(Maxwell)?

[1]http://gpgpu-sim.org/manual/index.php/Main_Page#Address_Decoding