That is for loading single elements from memory. Float, int must be 4-byte aligned, short must be 2-byte aligned, etc. or else the compiler will have to generate code to jiggle the bits to get it into a register correctly.
The discussion in this thread is about coalescing, where loading from multiple threads will fuse into a single memory transaction, for improved memory bandwidth. The multiple loads must be aligned to 16 elements (for thread 0), so for floats it is 64 bytes. For larger types (double, float4, etc) the alignment requirements for coalescing are bigger.
I am not sure I understand what you mean - the following code:
device type device;
type data = device[tid];
is about multiple threads reading sequential elements from an array, which should be coalesced into a single memory transaction. So this is exactly the case discussed by this thread.
However, I already found the answer in the old version of the guide as someone suggested, where it explicitly says that the base address must be aligned to 16*sizeof(element). Why they removed this in the new version is beyond any reason, especially since this limitation still holds.
Nvidia guys should really consider supplementing the guide because this is the only true source of information for programmers besides the code examples, which don’t explain many things.
I finally realized how to see coalescing through the visual profiler. I was shocked to see that it reports ~1,600,000 uncoalesced global reads versus ~400,000 coalesced global reads per iteration of the adders (similar numbers for memory aligned and tiled with fewer total reads for tiled).