# MiniMax-M3-AWQ on 4× GB10, fp8 KV, 262k context, adaptive reasoning, ~30 tok/s

**URL:** <https://forums.developer.nvidia.com/t/minimax-m3-awq-on-4x-gb10-fp8-kv-262k-context-adaptive-reasoning-30-tok-s/374175>\
**Category:** DGX Spark / GB10\
**Tags:** llama\
**Created:** [June 22, 2026, 10:30pm UTC](https://forums.developer.nvidia.com/t/minimax-m3-awq-on-4x-gb10-fp8-kv-262k-context-adaptive-reasoning-30-tok-s/374175 "2026-06-22T22:30:54Z")\
**Posts on this page:** 1\
**Showing post:** 17

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**Author:** ![tea24864](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@tea24864](https://forums.developer.nvidia.com/u/tea24864)\
**Post date:** [July 17, 2026, 2:41am UTC](https://forums.developer.nvidia.com/t/minimax-m3-awq-on-4x-gb10-fp8-kv-262k-context-adaptive-reasoning-30-tok-s/374175/17 "2026-07-17T02:41:12Z")

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> _**Note (2026-04-30):** NVIDIA later clarified on the [developer forum](https://forums.developer.nvidia.com/t/nvfp4-performance-update/367781) that this instruction actually does exist on GB10 — it requires the `sm_121a` target rather than `sm_121`. The observation in the original article was real (under `sm_121` it’s missing), but attributing it to “no circuit exists” was wrong._

The moment I read that note on the same post, I stopped reading it myself and sent Fable to read it.  
… And the epilogue confirms the conclusion is now stale: the same blog’s later posts show NVFP4 beating FP8 by ~1.5× for single-stream decode on a dense model (as a bandwidth/compression win) and NVFP4 W4A4 hitting 67 vs 52 tok/s against FP8 on an MoE once CUDA graphs were enabled. [[Benchmark] NVFP4 W4A4 beats FP8 on a DGX Spark MoE: 67 vs 52 tok/s once CUDA graphs fire — ai-muninn](https://ai-muninn.com/en/blog/dgx-spark-nvfp4-w4a4-moe-cudagraph)

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