I’m trying to connect Lattices MachXO3 CPLD Evaluation board to tegra CSI-2 interface on CSI_A. The CPLD is programmed with Lattice “Parallel to MIPI CSI-2 TX Bridge” reference design (http://www.latticesemi.com/csi2tx). The reference design also includes a test pattern generator. The reference design is configured to use 2 lanes. The pattern generator is configured for 1280x800 pixels RGB24 format. The CSI data and clock lanes show action, although I’m lacking high-speed oscilloscope to see the signals more clearly.
The Jetson TK1 is running custom compiled r21.5 kernel image. As suggested in the Tegra Linux Driver Package Development Guide for r21.4, I’ve written custom driver for the CPLD named machxo3csi2l2_v4l2 based on imx135_v4l2. Basically I’ve copied the imx135 sources and removed the I2C communication part since I don’t need it now because I can just program the CPLD the way I want to. I’ve also modified the board_ardbeg_sensors.c again by copying the imx135 code and modifying the tegra_camera_platform_data structure to use 2 lanes. I’ve also updated the device tree files tegra124-pm359-camera-a00.dtsi and tegra124-jetson_tk1-pmic-pm375-0000-c00-00.dtsi by copying imx135 sensor, renaming it and changing the bus I2C address to 0x15.
The Makefile and Kconfig have also been updated.
After copmiling kernel image, dtbs and modules, reflashing jetson, installing modules and rebooting I do:
sudo rmmod nvhost_vi
sudo modprobe machxo3csi2l2_v4l2
sudo modprobe tegra_camera
./yavta /dev/video0 -s1280x800 -Ftpg.argb
but i get an empty image. dmesg among other things gives the following:
[ 134.023402] vi vi.0: MIPI calibration timeout!
[ 134.024235] vi vi.0: CSI_A syncpt timeout, syncpt = 12, err = -11
I’ve tried googling “MIPI calibration timeout” but without luck.
Please note this is my first attempt at writing a linux driver.
I’m more inclined to belive this is a software problem rather than hardware.
Things I’ve tried:
-Tripple checked the connections between CPLD and Jetson
-Connecting/disconnecting the CPLD from jetson - no difference
-Setting continuous_clk in tegra_camera_platform_data structure in board_ardbeg_sensors.c
-Clocking CPLD form CAM1_MCLK
Any help would be much appreciated!