Mipi CSI-2 lanes swap on Jetpack 5

Is it possible to make csi-2 work with camera different lanes order?
I fount topic MIPI Lane swapping
I found some lane-swap related functions for C-PHY mode.

I tried to set brick_config.lane_swizzle to 0x15 (value that should swap lanes to right order) in the csi5_stream_set_config.
But xavier still doesn’t receive frames and getting errors:

     kworker/0:0-2846    [000] ....   336.091916: rtcpu_nvcsi_intr: tstamp:11067276474 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091917: rtcpu_nvcsi_intr: tstamp:11067282955 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091917: rtcpu_nvcsi_intr: tstamp:11067282955 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091918: rtcpu_vinotify_error: tstamp:11067297863 cch:0 vi:0 tag:CSIMUX_FRAME channel:0x00 frame:0 vi_tstamp:354153235616 data:0x00000000000000a2
     kworker/0:0-2846    [000] ....   336.091919: rtcpu_nvcsi_intr: tstamp:11067328325 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091919: rtcpu_nvcsi_intr: tstamp:11067328325 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091920: rtcpu_nvcsi_intr: tstamp:11067330959 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091920: rtcpu_nvcsi_intr: tstamp:11067330959 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091920: rtcpu_nvcsi_intr: tstamp:11067332150 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091921: rtcpu_nvcsi_intr: tstamp:11067332150 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091921: rtcpu_vinotify_error: tstamp:11067333511 cch:0 vi:0 tag:CHANSEL_NOMATCH channel:0x04 frame:0 vi_tstamp:354154504608 data:0x0000000000000289
     kworker/0:0-2846    [000] ....   336.091921: rtcpu_nvcsi_intr: tstamp:11067335731 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091922: rtcpu_nvcsi_intr: tstamp:11067335731 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004
     kworker/0:0-2846    [000] ....   336.091922: rtcpu_nvcsi_intr: tstamp:11067337583 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004

Also I tried other values for lane_swizzle, but camera still doesn’t work.

Is it possible to make work camera with with different lanes order?
I’m using 'serial_c" with 4-lane mode. How to set NVCSI_PHY_1_NVCSI_CIL_LANE_SWIZZLE_CTRL_0 properly?

There’s CHANSEL_NOMATCH could be incorrect embedded_data_height in device tree and below tells the CRC error.

Does the trace log different while modify the lane_swizzle?

CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:0 status:0x00000004

I’m sure that camera doesn’t send any embedded data. It sending only YUYV(dt = 0x1e) frames with 1920x1080 size.

CHANSEL_NOMATCH and CSIMUX_FRAME data value change for some lane_swizzle, but with any lane_swizzle value I have errors in trace and sometimes xavier reboots after CBB-error

Sorry for the late response.
Is this still an issue to support? Any result can be shared?

The error tell the payload CRC error.

When lanes are in wrong order - CRC will have error, it is expected behavior, I suppose.
Is it possible to get received mipi csi packet headers? It would help to understand does brick_config.lane_swizzle working.

The lane_swizzle is working for v4l2 usage but argus pipeline.