MIPI CSI-2 Version Compatibility

Hello

Jetson xavier is support MIPI CSI-2 v2.0, in our design chipset indicates support CSI-2 v1.3.

Could xavier Backward compatible to v1.3?

Thanks,
John

Hi,
Yes, it’s compatible with v1.3

Regarding to VC-ID bits, v1.3 is 2-bit, v2.0 is 4-bit, does it auto switch to?

Need to set the REG NVCSI_STREAM_X_PH_CHK_CTRL_0.CFG_PH_16_VC to disable for the VC ID support.

nvcsi@15a00000 defined from DTB.

NVCSI_STREAM_0_PH_CHK_CTRL_0 byte offset 0x10194 defined from TRM document.

When read the register system hangs up.

Does the REG location wrong?

The address is 0x15a10194 you can’t access the REG without disable the powergat.
You should access this address by the csi5_fops.c

REG could be read and wrote success, how to verify the 16-bit VC has been disabled?

what’s the function of cfg_swreset ? Is it reset all of nvcsi stream x bit?

It control the reset of stream
write 1 to reset